LMG1205 Datasheet, PDF (13/24 Pages) Texas Instruments – 100-V, 1.2-A, 5-A, Half-Bridge Gate Driver for Enhancement Mode GaN FETs

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LMG1205
SNOSD37 – MARCH 2017
8.2 Typical Application
The circuit in Figure 16 shows a synchronous buck converter to evaluate LMG1205. Detailed synchronous buck
converter specifications are listed in Design Requirements. Optimization of he power loop (loop impedance from
VIN capacitor to PGND) is critical to the performance of the design. Having a high power loop inductance causes
significant ringing in the SW node and also causes an associated power loss. For more information, please refer
to Related Documentation.
0.1 F
VIN
HB
Rgh
HOH
VDD
HOL
1F
HI
HS
LMG1205
Rgl
LI
LOH
LOL
VSS
VOUT
COUT
Copyright © 2017, Texas Instruments Incorporated
Figure 16. Application Circuit
8.2.1 Design Requirements
When designing a synchronous buck converter application that incorporates the LMG1205 gate driver and GaN
power FETs, some design considerations must be evaluated first to make the most appropriate selection. Among
these considerations are the input voltages, passive components, operating frequency, and controller selection.
Table 4 shows some sample values for a typical application. See Power Supply Recommendations, Layout, and
Power Dissipation for other key design considerations for the LMG1205.
Table 4. Design Parameters
PARAMETER
Half-bridge input supply voltage,
V_IN
Output voltage, V_OUT
Output current
Dead time
Inductor
Switching frequency
SAMPLE VALUE
48 V
12 V
8A
8 ns
4.7 µH
1 MHz
8.2.2 Detailed Design Procedure
This procedure outlines the design considerations of LMG1205 in a synchronous buck converter with
enhancement mode GaN FET. For additional design help, see Related Documentation.
8.2.2.1 VDD Bypass Capacitor
The VDD bypass capacitor provides the gate charge for the low-side and high-side transistors and to absorb the
reverse recovery charge of the bootstrap diode. The required bypass capacitance can be calculated with
Equation 1.
C_VDD ! ^QgH
Q_gL
'V
Q_rr
where
• Q_gH and Q_gL are gate charge of the high-side and low-side transistors, respectively
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