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4.5 Pin Diagram – YFV (Chip Scale, DSBGA) Package
CC2640R2F
SWRS204 – DECEMBER 2016
A1
A2
A3
A4
B1
B2
B3
B4
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
E6
F1
F2
F3
F4
F5
F6
Figure 4-3. YFV (2.7-mm × 2.7-mm) Pinout, Top View
4.6 Signal Descriptions – YFV (Chip Scale, DSBGA) Package
NAME
DCDC_SW
DCOUPL
DIO_0
DIO_1
DIO_2
DIO_3
DIO_4
DIO_5
DIO_6
DIO_7
DIO_8
DIO_9
DIO_10
DIO_11
DIO_12
DIO_13
JTAG_TMSC
JTAG_TCKC
RESET_N
RF_N
RF_P
Table 4-3. Signal Descriptions – YFV Package
NO.
TYPE
DESCRIPTION
D1
Power
Output from internal DC-DC⁽¹⁾
F3
Power
1.27-V regulated digital-supply decoupling⁽²⁾
C5
Digital I/O
GPIO, Sensor Controller
F6
Digital I/O
GPIO, Sensor Controller
D5
Digital I/O
GPIO, Sensor Controller, high-drive capability
E5
Digital I/O
GPIO, Sensor Controller, high-drive capability
F5
Digital I/O
GPIO, Sensor Controller, high-drive capability
E3
Digital I/O
GPIO, High-drive capability, JTAG_TDO
F1
Digital I/O
GPIO, High-drive capability, JTAG_TDI
D2
Digital/Analog I/O GPIO, Sensor Controller, Analog
D3
Digital/Analog I/O GPIO, Sensor Controller, Analog
A1
Digital/Analog I/O GPIO, Sensor Controller, Analog
C2
Digital/Analog I/O GPIO, Sensor Controller, Analog
B2
Digital/Analog I/O GPIO, Sensor Controller, Analog
D4
Digital/Analog I/O GPIO, Sensor Controller, Analog
B3
Digital/Analog I/O GPIO, Sensor Controller, Analog
E4
Digital I/O
JTAG TMSC, high-drive capability
F2
Digital I/O
JTAG TCKC
E2
Digital input Reset, active-low. No internal pullup.
B6
RF I/O
Negative RF input signal to LNA during RX
Negative RF output signal to PA during TX
B5
RF I/O
Positive RF input signal to LNA during RX
Positive RF output signal to PA during TX
(1) For more details, see the technical reference manual (listed in Section 8.3).
(2) Do not supply external circuitry from this pin.
Copyright © 2016, Texas Instruments Incorporated
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Terminal Configuration and Functions
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