TMS320VC5502 Datasheet, PDF (98/189 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004
www.ti.com
3.14 Internal Ports and System Registers
The 5502 includes three internal ports that interface the CPU core with the peripheral modules. Although
these ports cannot be directly controlled by user code, the registers associated with each port can be used
to monitor a number of error conditions that could be generated through illegal operation of the 5502. The
port registers are described in the following sections.
The 5502 also includes two registers that can be used to monitor and control several aspects of the
interface between the CPU and the system-level peripherals, these registers are also described in the
following sections.
3.14.1 XPORT Interface
The XPORT interfaces the CPU core to all peripheral modules. The XPORT will generate bus errors for
invalid accesses to any registers that fall under the ranges shown in Table 3-48. The INTERREN bit of the
XPORT Configuration Register (XCR) controls the bus error feature of the XPORT. The INTERR bit of the
XPORT Bus Error Register (XERR) is set to '1' when an error occurs during an access to a register listed
in Table 3-48. The EBUS and DBUS bits can be used to distinguish whether the error occurred during a
write or read access.
Table 3-48. I/O Addresses Under Scope of XPORT
I/O ADDRESS RANGE
0x0000–0x03FF
0x1400–0x17FF
0x2000–0x23FF
The PERITO bit of the XERR is used to indicate that a CPU, DMA, or HPI access to a disabled/idled
peripheral module has generated a time-out error. The time-out error feature is enabled through the
PERITOEN bit of the Time-Out Control Register (TOCR). A time-out error is generated when 512 clock
cycles pass without a response from the peripheral register.
The XPORT can be placed into idle by setting the XPORTI bit of the Idle Control Register (ICR) and
executing the IDLE instruction. When the XPORT is in idle, it will stop accepting new peripheral module
requests and it will also not check for internal I/O bus errors. If there is a request from the CPU core or a
peripheral module, the XPORT will not respond and hang. The ICR register will generate a bus error if the
XPORT is idled without the CPU or Master Port domains being in idle mode.
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Functional Overview