TMS320VC5502 Datasheet, PDF (158/189 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004
5.15 Multichannel Buffered Serial Port (McBSP) Timings
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5.15.1 McBSP Transmit and Receive Timings
Table 5-31 and Table 5-32 assume testing over recommended operating conditions (see Figure 5-32 and
Figure 5-33).
Table 5-31. McBSP Transmit and Receive Timing Requirements⁽¹⁾⁽²⁾
VC5502-200
NO.
VC5502-300 _UNIT
MIN MAX
M11
M12
M13
M14
t_c(CKRX)
t_w(CKRX)
t_r(CKRX)
t_f(CKRX)
M15 t_su(FRH-CKRL)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Rise time, CLKR/X
Fall time, CLKR/X
Setup time, external FSR high before CLKR low
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
2P
P–2
5
1
ns
ns
5 ns
5 ns
ns
M16 t_h(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int
1
ns
CLKR ext
6
M17 t_su(DRV-CKRL)
Setup time, DR valid before CLKR low
CLKR int
3
ns
CLKR ext
1
M18 t_h(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int
1
ns
CLKR ext
6
M19 t_su(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKX int
CLKX ext
5
ns
1
M20 t_h(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKX int
CLKX ext
1
ns
6
(1) Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that
signal are also inverted.
(2) P = (Divider2 Ratio)/(CPU Clock Frequency) in ns. For example, when running parts at 300 MHz with the slow peripheral domain at 1/2
the CPU clock frequency, use P = 2/300 MHz = 6.66 ns.
158 Specifications