TMS320VC5502 Datasheet, PDF (23/189 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

www.ti.com
TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004
PIN
NAME
C0
C1
C2
Table 2-4. Signal Descriptions (continued)
MULTIPLEXED
SIGNAL NAME
PGPIO20
EMIF.ARE/SADS/
SDCAS/SRE
PGPIO21
EMIF.AOE/SOE/
SDRAS
PGPIO22
EMIF.AWE/SWE/
SDWE
PIN
TYPE ⁽¹⁾
I/O/Z
I/O/Z
O/Z
I/O/Z
I/O/Z
O/Z
I/O/Z
I/O/Z
O/Z
OTHER ⁽²⁾
FUNCTION
Parallel Port — Control Pins
The C0 pin of the Parallel Port serves one of two functions: parallel general-purpose
input/output (PGPIO) signal PGPIO20 or external memory interface control signal
EMIF.ARE/SADS/SDCAS/SRE. The function of the C0 pin is determined by the
state of the GPIO6 pin during reset. The C0 pin is set to PGPIO20 if GPIO6 is low
during reset. The C0 pin is set to EMIF.ARE/SADS/SDCAS/SRE if GPIO6 is high
during reset. The function of the C0 pin will be set once the device is taken out of
reset (RESET pin transitions from a low to high state).
C, D, E, F,
G, H, M
Parallel general-purpose I/O. PGPIO20 is selected when GPIO6 is low during
reset. The PGPIO20 signal is configured as an input after reset.
EMIF control pin. EMIF.ARE/SADS/SDCAS/SRE is selected when GPIO6 is high
during reset. The EMIF.ARE/SADS/SDCAS/SRE signal is in a high-impedance state
during reset and is set to output after reset with an output value of 1.
The EMIF.ARE/SADS/SDCAS/SRE signal serves four different functions when used
by the EMIF: asynchronous memory read-enable (EMIF.ARE), synchronous memory
address strobe (EMIF.SADS), SDRAM column-address strobe (EMIF.SDCAS), and
synchronous read-enable (EMIF.SRE) (selected by RENEN in the CE Secondary
Control Register 1).
The C1 pin of the Parallel Port serves one of two functions: parallel general-purpose
input/output (PGPIO) signal PGPIO21 or external memory interface control signal
EMIF.AOE/SOE/SDRAS. The function of the C1 pin is determined by the state of
the GPIO6 pin during reset. The C1 pin is set to PGPIO21 if GPIO6 is low during
reset. The C1 pin is set to EMIF.AOE/SOE/SDRAS if GPIO6 is high during reset.
The function of the C1 pin will be set once the device is taken out of reset (RESET
pin transitions from a low to high state).
C, D, E, F,
G, H, M
Parallel general-purpose I/O. PGPIO21 is selected when GPIO6 is low during
reset. The PGPIO21 signal is configured as an input after reset.
EMIF control pin. EMIF.AOE/SOE/SDRAS is selected when GPIO6 is high during
reset. The EMIF.AOE/SOE/SDRAS signal is in a high-impedance state during reset
and is set to output after reset with an output value of 1.
The EMIF.AOE/SOE/SDRAS signal serves three different functions when used by
the EMIF: asynchronous memory output-enable (EMIF.AOE), synchronous memory
output-enable (EMIF.SOE), and SDRAM row-address strobe (EMIF.SDRAS).
The C2 pin of the Parallel Port serves one of two functions: parallel general-purpose
input/output (PGPIO) signal PGPIO22 or external memory interface control signal
EMIF.AWE/SWE/SDWE. The function of the C2 pin is determined by the state of the
GPIO6 pin during reset. The C2 pin is set to PGPIO22 if GPIO6 is low during reset.
The C2 pin is set to EMIF.AWE/SWE/SDWE if GPIO6 is high during reset. The
function of the C2 pin will be set once the device is taken out of reset (RESET pin
transitions from a low to high state).
C, D, E, F,
G, H, M
Parallel general-purpose I/O. PGPIO22 is selected when GPIO6 is low during
reset. The PGPIO22 signal is configured as an input after reset.
EMIF control pin. EMIF.AWE/SWE/SDWE is selected when GPIO6 is high during
reset. The EMIF.AWE/SWE/SDWE signal is in a high-impedance state during reset
and is set to output after reset with an output value of 1.
The EMIF.AWE/SWE/SDWE signal serves three different functions when used by
the EMIF: asynchronous memory write-enable (EMIF.AWE), synchronous memory
write-enable (EMIF.SWE), and SDRAM write-enable (EMIF.SDWE).
Introduction
23