TMS320VC5502 Datasheet, PDF (142/189 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004
www.ti.com
5.7.3 Synchronous DRAM Timings
Table 5-13 and Table 5-14 assume testing over recommended operating conditions (see Figure 5-13 through
Figure 5-20).
NO.
SD6
SD7
t_{su(EDV-EKO1H)}
t_h(EKO1H-EDV)
Table 5-13. Synchronous DRAM Cycle Timing Requirements
Setup time, read EMIF.Dx valid before ECLKOUT1 high
Hold time, read EMIF.Dx valid after ECLKOUT1 high
VC5502-200
VC5502-300
MIN MAX
2
2
UNIT
ns
ns
NO.
SD1
SD2
SD3
SD4
SD5
SD8
SD9
SD10
SD11
SD12
SD13
t_d(EKO1H-CEV)
t_d(EKO1H-BEV)
t_{d(EKO1H-BEIV)}
t_d(EKO1H-EAV)
t_{d(EKO1H-EAIV)}
t_{d(EKO1H-CASV)}
t_d(EKO1H-EDV)
t_{d(EKO1H-EDIV)}
t_d(EKO1H-WEV)
t_{d(EKO1H-RASV)}
t_{d(EKO1H-CKEV)}
Table 5-14. Synchronous DRAM Cycle Switching Characteristics
PARAMETER
Delay time, ECLKOUT1 high to EMIF.CEx valid/invalid
Delay time, ECLKOUT1 high to EMIF.BEx valid
Delay time, ECLKOUT1 high to EMIF.BEx invalid
Delay time, ECLKOUT1 high to EMIF.Ax valid
Delay time, ECLKOUT1 high to EMIF.Ax invalid
Delay time, ECLKOUT1 high to EMIF.SDCAS valid
Delay time, ECLKOUT1 high to EMIF.Dx valid
Delay time, ECLKOUT1 high to EMIF.Dx invalid
Delay time, ECLKOUT1 high to EMIF.SDWE valid
Delay time, ECLKOUT1 high to EMIF.SDRAS valid
Delay time, ECLKOUT1 high to EMIF.SDCKE valid
VC5502-200
VC5502-300
MIN MAX
0.8
7
7
0.8
7
0.8
0.8
7
7
0.8
0.8
7
0.8
7
0.8
7
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
142 Specifications