TMS320VC5502 Datasheet, PDF (56/189 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004
Table 3-10. Recommended Crystal Parameters
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FREQUENCY RANGE (MHz)
20-15
15-12
12-10
10-8
8-6
6-5
MAXIMUM ESR
SPECIFICATIONS (Ω)
40
40
40
60
60
80
C_LOAD (pF)
10
16
16
18
18
18
MAXIMUM
C_SHUNT (pF)
7
7
7
7
7
7
R_S (kΩ)
0
0
2.8
2.2
8.8
14
The recommended ESR is presented as a maximum, and theoretically, a crystal with a lower maximum
ESR might seem to meet these specifications. However, it is recommended that crystals with actual
maximum ESR specifications as shown in Table 3-10 be used since this will result in maximum crystal
performance reliability.
The internal oscillator can be set to power-down mode through the use of the OSCPWRDN bit in the PLL
Control/Status Register (PLLCSR). If the internal oscillator and the external crystal are generating the
input clock for the DSP (CLKMD0 = 0), the internal oscillator will be set to power-down mode when the
OSCPWRDN bit is set to 1 and the clock generator is set to its idle mode (CLKIS bit of the IDLE Status
Register (ISTR) becomes 1). If the X2/CLKIN pin is supplying the input clock to the DSP (CLKMD0 = 1),
the internal oscillator will be set to power-down immediately after the OSCPWRDN bit is set to 1.
The 5502 has internal circuitry that will count down a predetermined number of clock cycles (41,032
reference clock cycles) to allow the oscillator input to become stable after waking up from power-down
state or after reset. If a reset is asserted, program flow will start after all stabilization periods have expired;
this includes the oscillator stabilization period only if GPIO4 is low at reset. If the oscillator is coming out of
power-down mode, program flow will start immediately after the oscillator stabilization period has
completed. See Section 3.10.6, Reset Sequence, for more details on program flow after reset or after
oscillator power-down. See Section 3.11, Idle Control, for more information on the oscillator power-down
mode.
3.10.1.2 Clock Generation With PLL Disabled (Bypass Mode, Default)
After reset, the PLL multiplier (M1) and its divider (D0) will be bypassed by default and the input clock to
point C in Figure 3-14 will be taken from, depending on the state of the GPIO4 pin after reset, either the
internal oscillator or the X2/CLKIN pin. The PLL can be taken out of bypass mode as described in
Section 3.10.4.1, C55x Subsystem Clock Group.
3.10.1.3 Clock Generation With PLL Enabled (PLL Mode)
When not in bypass mode, the frequency of the input clock can be divided down by a programmable
divider (D0) by any factor from 1 to 32. The output clock of the divider can be multiplied by any factor from
2 to 15 through a programmable multiplier (M1). The divider factor can be set through the PLLDIV0 bit of
the PLL Divider 0 Register. The multiplier factor can be set through the PLLM bits of the PLL Multiplier
Control Register.
There is a specific minimum and maximum reference clock (PLLREF) and output clock (PLLOUT) for the
block labeled "PLL" in Figure 3-12, as well as for the C55x Core clock (CLKOUT3), the Fast Peripherals
clock (SYSCLK1), the Slow Peripherals clock (SYSCLK2), and the EMIF internal clock (SYSCLK3). The
clock generator must not be configured to exceed any of these constraints (certain combinations of
external clock input, internal dividers, and PLL multiply ratios might not be supported). See Table 3-11 for
the PLL clock input and output frequency ranges.
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Functional Overview