TMS320VC5502 Datasheet, PDF (100/189 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004
www.ti.com
3.14.1.2 XPORT Bus Error Register (XERR)
The XPORT Bus Error Register bit layout is shown in Figure 3-45 and the bits are described in
Table 3-50.
15
14
13
12
11
8
INTERR
Reserved
PERITO
Reserved
R, 0
R, 00
R, 0
R, 0000
7
5
Reserved
R, 000
LEGEND: R = Read, W = Write, n = value at reset
4
EBUS
R, 0
3
DBUS
R, 0
2
0
Reserved
R, 000
Figure 3-45. XPORT Bus Error Register Layout (0x0102)
BIT NAME
INTERR
Reserved
PERITO
Reserved
EBUS
DBUS
Reserved
Table 3-50. XPORT Bus Error Register Bit Field Description
BIT NO.
15
14–13
12
11–5
4
3
2–0
ACCESS
R
R
R
R
R
R
R
RESET VALUE
0
00
0
0000000
0
0
000
DESCRIPTION
INTERR bit
• INTERR = 0: No error
• INTERR = 1: An error occurred during an access to one of the
registers listed in Table 3-48.
Reserved
PERITO bit
• PERITO = 0: No error
• PERITO = 1: A time-out error occurred during an access to a
peripheral register.
Reserved
EBUS error bit⁽¹⁾
• EBUS = 0: No error
• EBUS = 1: An error occurred during an EBUS access (write) to
one of the registers listed in Table 3-48.
DBUS error bit⁽¹⁾
• DBUS = 0: No error
• DBUS = 1: An error occurred during a DBUS access (read) to
one of the registers listed in Table 3-48.
Reserved
(1) See the TMS320C55x DSP CPU Reference Guide (literature number SPRU371) for more information on the D-bus and E-bus.
3.14.2 DPORT Interface
The DPORT interfaces the CPU to the EMIF module. The DPORT is capable of enabling write posting on
the EMIF module. Write posting prevents stalls to the CPU during external memory writes. Two write
posting registers, which are freely associated with E and F bus writes, exist within the DPORT and are
used to store the write address and data so that writes can be zero wait state for the CPU. External
memory writes will not generate stalls to the CPU unless the two write posting registers are filled. Write
posting is enabled by setting the WPE bit of the DCR to 1.
The EMIFTO bit of the DERR is used to indicate that a CPU, DMA, HPI, or IPORT access to external
memory has generated a time-out error. The time-out error feature is enabled through the EMIFTOEN bit
of the Time-Out Control Register (TOCR). This function is not recommended during normal operation of
the 5502.
100 Functional Overview