TMS320VC5502 Datasheet, PDF (26/189 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

TMS320VC5502
Fixed-Point Digital Signal Processor
SPRS166H – APRIL 2001 – REVISED NOVEMBER 2004
www.ti.com
PIN
NAME
C12
C13
C14
C15
ECLKIN
MULTIPLEXED
SIGNAL NAME
PGPIO32
EMIF.SDCKE
PGPIO33
EMIF.SOE3
PGPIO34
EMIF.HOLD
PGPIO35
EMIF.HOLDA
Table 2-4. Signal Descriptions (continued)
PIN
TYPE ⁽¹⁾
I/O/Z
I/O/Z
O/Z
I/O/Z
I/O/Z
O/Z
I/O/Z
I/O/Z
I
I/O/Z
I/O/Z
O/Z
I
OTHER ⁽²⁾
FUNCTION
The C12 pin of the Parallel Port serves one of two functions: parallel gen-
eral-purpose input/output (PGPIO) signal PGPIO32 or external memory interface
control signal EMIF.SDCKE. The function of the C12 pin is determined by the state
of the GPIO6 pin during reset. The C12 pin is set to PGPIO32 if GPIO6 is low during
reset. The C12 pin is set to EMIF.SDCKE if GPIO6 is high during reset. The function
C, D, E, F,
G, H, M
of the C12 pin will be set once the device is taken out of reset (RESET pin
transitions from a low to high state).
Parallel general-purpose I/O. PGPIO32 is selected when GPIO6 is low during
reset. The PGPIO32 signal is configured as an input after reset.
EMIF SDRAM clock-enable. EMIF.SDCKE is selected when GPIO6 is high during
reset. The EMIF.SDCKE signal is in a high-impedance state during reset and is set
to output after reset with an output value of 1.
The C13 pin of the Parallel Port serves one of two functions: parallel gen-
eral-purpose input/output (PGPIO) signal PGPIO33 or external memory interface
control signal EMIF.SOE3. The function of the C13 pin is determined by the state of
the GPIO6 pin during reset. The C13 pin is set to PGPIO33 if GPIO6 is low during
reset. The C13 pin is set to EMIF.SOE3 if GPIO6 is high during reset. The function
of the C13 pin will be set once the device is taken out of reset (RESET pin
C, D, E, F, transitions from a low to high state).
G, H, M _{Parallel general-purpose I/O. PGPIO33 is selected when GPIO6 is low during}
reset. The PGPIO33 signal is configured as an input after reset.
EMIF synchronous memory output-enable for CE3. EMIF.SOE3 is selected when
GPIO6 is high during reset. The EMIF.SOE3 signal is in a high-impedance state
during reset and is set to output after reset with an output value of 1.
The EMIF.SOE3 is intended for glueless FIFO interface.
F, G, H, J,
M
The C14 pin of the Parallel Port serves one of two functions: parallel gen-
eral-purpose input/output (PGPIO) signal PGPIO34 or external memory interface
control signal EMIF.HOLD. The function of the C14 pin is determined by the state of
the GPIO6 pin during reset. The C14 pin is set to PGPIO34 if GPIO6 is low during
reset. The C14 pin is set to EMIF.HOLD if GPIO6 is high during reset. The function
of the C14 pin will be set once the device is taken out of reset (RESET pin
transitions from a low to high state).
Parallel general-purpose I/O. PGPIO34 is selected when GPIO6 is low during
reset. The PGPIO34 signal is configured as an input after reset.
EMIF hold request. EMIF.HOLD is selected when GPIO6 is high during reset.
EMIF.HOLD is asserted by an external host to request control of the address, data,
and control signals.
The C15 pin of the Parallel Port serves one of two functions: parallel gen-
eral-purpose input/output (PGPIO) signal PGPIO35 or external memory interface
control signal EMIF.HOLDA. The function of the C15 pin is determined by the state
of the GPIO6 pin during reset. The C15 pin is set to PGPIO35 if GPIO6 is low during
reset. The C15 pin is set to EMIF.HOLDA if GPIO6 is high during reset. The function
of the C15 pin will be set once the device is taken out of reset (RESET pin
transitions from a low to high state).
C, D, F, G,
H, M
Parallel general-purpose I/O. PGPIO35 is selected when GPIO6 is low during
reset. The PGPIO35 signal is configured as an input after reset.
EMIF hold acknowledge. EMIF.HOLDA is selected when GPIO6 is high during
reset. The EMIF.HOLDA signal is in a high-impedance state during reset and is set
to output after reset with an output value of '1'.
EMIF.HOLDA is asserted by the DSP to indicate that the DSP is in the HOLD state
and that the EMIF address, data, and control signals are in a high-impedance state,
allowing the external memory interface to be accessed by other devices.
EMIF — Clock Pins
C, L
External EMIF input clock. ECLKIN is selected as the input clock to the EMIF
when EMIFCLKS is high.
26
Introduction