AM1705_1004 Datasheet, PDF (96/155 Pages) Texas Instruments – AM1705 ARM Microprocessor

AM1705
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
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6.18.2 SPI Electrical Data/Timing
6.18.2.1 Serial Peripheral Interface (SPI) Timing
Table 6-49 through Table 6-64 assume testing over recommended operating conditions (see Figure 6-31
through Figure 6-34).
Table 6-49. General Timing Requirements for SPI0 Master Modes⁽¹⁾
No.
PARAMETER
1 t_c(SPC)M
Cycle Time, SPI0_CLK, All Master Modes
2 t_w(SPCH)M
3 t_w(SPCL)M
Pulse Width High, SPI0_CLK, All Master Modes
Pulse Width Low, SPI0_CLK, All Master Modes
Polarity = 0, Phase = 0,
to SPI0_CLK rising
Polarity = 0, Phase = 1,
4
t_{d(SIMO_SPC)M}
Delay, initial data bit valid on SPI0_SIMO ^{to SPI0_CLK rising}
after initial edge on SPI0_CLK⁽²⁾
Polarity = 1, Phase = 0,
to SPI0_CLK falling
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK rising
Delay, subsequent bits valid on
5 t_{d(SPC_SIMO)M} SPI0_SIMO after transmit edge of
SPI0_CLK
Polarity = 0, Phase = 1,
from SPI0_CLK falling
Polarity = 1, Phase = 0,
from SPI0_CLK falling
Polarity = 1, Phase = 1,
from SPI0_CLK rising
Polarity = 0, Phase = 0,
from SPI0_CLK falling
6
t_{oh(SPC_SIMO)M}
Output hold time, SPI0_SIMO valid
afterreceive edge of SPI0_CLK
Polarity = 0, Phase = 1,
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
Polarity = 0, Phase = 0,
to SPI0_CLK falling
7
t_{su(SOMI_SPC)M}
Input Setup Time, SPI0_SOMI valid
beforereceive edge of SPI0_CLK
Polarity = 0, Phase = 1,
to SPI0_CLK rising
Polarity = 1, Phase = 0,
to SPI0_CLK rising
Polarity = 1, Phase = 1,
to SPI0_CLK falling
Polarity = 0, Phase = 0,
from SPI0_CLK falling
Polarity = 0, Phase = 1,
8
t_{ih(SPC_SOMI)M}
Input Hold Time, SPI0_SOMI valid after
receive edge of SPI0_CLK
from SPI0_CLK rising
Polarity = 1, Phase = 0,
from SPI0_CLK rising
Polarity = 1, Phase = 1,
from SPI0_CLK falling
MIN
greater of 2P or
20 ns
0.5t_c(SPC)M - 1
0.5t_c(SPC)M - 1
MAX
UNIT
256P ns
ns
ns
5
- 0.5t_c(SPC)M + 5
ns
5
- 0.5t_c(SPC)M + 5
5
5
ns
5
5
0.5t_c(SPC)M -3
0.5t_c(SPC)M -3
ns
0.5t_c(SPC)M -3
0.5t_c(SPC)M -3
0
0
ns
0
0
5
5
ns
5
5
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPI0_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPI0_SOMI.
96
Peripheral Information and Electrical Specifications
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