AM1705_1004 Datasheet, PDF (104/155 Pages) Texas Instruments – AM1705 ARM Microprocessor

AM1705
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
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Table 6-60. Additional⁽¹⁾ SPI1 Master Timings, 4-Pin Chip Select Option^{(2) (3)}
No.
19 t_{d(SCS_SPC)M}
20 t_{d(SPC_SCS)M}
PARAMETER
Delay from SPI1_SCS active to first
SPI1_CLK^{(4) (5)}
Delay from final SPI1_CLK edge to master
deasserting SPI1_SCS ^{(6) (7)}
Polarity = 0, Phase =
0,
to SPI1_CLK rising
Polarity = 0, Phase =
1,
to SPI1_CLK rising
Polarity = 1, Phase =
0,
to SPI1_CLK falling
Polarity = 1, Phase =
1,
to SPI1_CLK falling
Polarity = 0, Phase =
0,
from SPI1_CLK
falling
Polarity = 0, Phase =
1,
from SPI1_CLK
falling
Polarity = 1, Phase =
0,
from SPI1_CLK rising
Polarity = 1, Phase =
1,
from SPI1_CLK rising
MIN
MAX UNIT
2P -5
0.5t_c(SPC)M + 2P -5
ns
2P -5
0.5t_c(SPC)M + 2P -5
0.5t_c(SPC)M + P - 3
P-3
ns
0.5t_c(SPC)M + P -3
P-3
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-57 ).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_SCS assertion.
(5) This delay can be increased under software control by the register bit field SPIDELAY.C2TDELAY[4:0].
(6) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(7) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
Table 6-61. Additional⁽¹⁾ SPI1 Master Timings, 5-Pin Option^{(2) (3)}
No.
18 t_{d(SPC_ENA)M}
20 t_{d(SPC_SCS)M}
PARAMETER
Polarity = 0, Phase = 0,
Max delay for slave to ^{from SPI1_CLK falling}
deassert SPI1_ENA
after final SPI1_CLK
edge to ensure
master does not
begin the next
transfer. ⁽⁴⁾
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
Polarity = 0, Phase = 0,
from SPI1_CLK falling
Delay from final
SPI1_CLK edge to
master deasserting
SPI1_SCS ^{(5) (6)}
Polarity = 0, Phase = 1,
from SPI1_CLK falling
Polarity = 1, Phase = 0,
from SPI1_CLK rising
Polarity = 1, Phase = 1,
from SPI1_CLK rising
MIN
0.5t_c(SPC)M + P -3
P-3
0.5t_c(SPC)M+ P -3
P-3
MAX
UNIT
0.5t_c(SPC)M+P+5
P+5
ns
0.5t_c(SPC)M+P+5
P+5
ns
(1) These parameters are in addition to the general timings for SPI master modes ( Table 6-58 ).
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes.
(4) In the case where the master SPI is ready with new data before SPI1_ENA deassertion.
(5) Except for modes when SPIDAT1.CSHOLD is enabled and there is additional data to transmit. In this case, SPI1_SCS will remain
asserted.
(6) This delay can be increased under software control by the register bit field SPIDELAY.T2CDELAY[4:0].
104 Peripheral Information and Electrical Specifications
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