AM1705_1004 Datasheet, PDF (4/155 Pages) Texas Instruments – AM1705 ARM Microprocessor

AM1705
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
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1.3 Description
The device is a low-power ARM microprocessor based on an ARM926EJ-S™.
The device enables OEMs and ODMs to quickly bring to market devices featuring robust operating
systems support, rich user interfaces, and high processing performance life through the maximum
flexibility of a fully integrated mixed processor solution.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and
memory system can operate continuously.
The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory
Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and
16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core
also has a 8KB RAM (Vector Table) and 64KB ROM.
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output
(MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 3 multichannel audio serial port (McASP)
with serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one configurable as
watchdog); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable
interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with RTS
and CTS); 3 enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced
capture (eCAP) module peripherals which can be configured as 3 capture inputs or 3 auxiliary pulse width
modulator (APWM) outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external
memory interfaces: an asynchronous and SDRAM external memory interface (EMIFA) for slower
memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the device and the
network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps
in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is
available for PHY configuration.
TheI2C, SPI, and USB2.0 ports allow the device to easily control peripheral devices and/or communicate
with host processors.
The rich peripheral set provides the ability to control external peripheral devices and communicate with
external processors. For details on each of the peripherals, see the related sections later in this document
and the associated peripheral reference guides.
The device has a complete set of development tools for the ARM. These include C compilers and a
Windows™ debugger interface for visibility into source code execution.
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AM1705 ARM Microprocessor
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