AM1705_1004 Datasheet, PDF (37/155 Pages) Texas Instruments – AM1705 ARM Microprocessor

AM1705
www.ti.com
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
6.3 Power Supplies
6.3.1 Power-on Sequence
The device should be powered-on in the following order:
• 2a) CVDD core logic supply
• 2b) Other 1.2V logic supplies (RVDD, PLL0_VDDA). Groups 2a) and 2b) may be powered up together
or 2a) first followed by 2b).
• 3) All 1.8V IO supplies (USB0_VDDA18).
• 4) All digital IO and analog 3.3V PHY supplies (DVDD, USB0_VDDA33). USB0_VDDA33 is not
required if USB0 is not used and may be left unconnected.
There is no specific required voltage ramp rate for any of the supplies.
RESET must be maintained active until all power supplies have reached their nominal values.
Note: Future devices may support higher performance at a higher core logic voltage (CVDD). If future
migration is desired, the current design should provide separate supplies for 2a) and 2b). If not, then 2a)
and 2b) may be provided by a single supply.
6.3.2 Power-off Sequence
The power supplies can be powered-off in any order as long as the 3.3V supplies do not remain powered
with the other supplies unpowered.
6.4 Unused USB0 (USB2.0) Pin Configurations
Table 6-1. Unused USB0 Pin Configurations
SIGNAL NAME
USB0_DM
USB0_DP
USB0_VDDA33
USB0_VDDA18
USB0_VBUS
USB0_VDDA12
AHCLKX0/AHCLKX2/USB_REFCLKIN/
GP2[11]
Configuration
(When USB0 is not used)
No connect
No connect
No connect
No connect
No connect
No connect
No connect or use as alternate function
6.5 Reset
6.5.1 Power-On Reset (POR)
A power-on reset (POR) is required to place the device in a known good state after power-up. Power-On
Reset is initiated by bringing RESET and TRST low at the same time. POR sets all of the device internal
logic to its default state. All pins are 3-stated .
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
Copyright © 2010, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
37
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