AM1705_1004 Datasheet, PDF (52/155 Pages) Texas Instruments – AM1705 ARM Microprocessor

AM1705
SPRS657A – FEBRUARY 2010 – REVISED APRIL 2010
BYTE ADDRESS
0x01E2 60A8
0x01E2 60AC
Table 6-9. GPIO Registers (continued)
ACRONYM
CLR_FAL_TRIG67
INTSTAT67
REGISTER DESCRIPTION
GPIO Banks 6 and 7 Clear Falling Edge Interrupt Register
GPIO Banks 6 and 7 Interrupt Status Register
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6.9.2 GPIO Peripheral Input/Output Electrical Data/Timing
Table 6-10. Timing Requirements for GPIO Inputs⁽¹⁾ (see Figure 6-10)
No.
PARAMETER
MIN
MAX
UNIT
1 t_w(GPIH)
2 t_w(GPIL)
Pulse duration, GPn[m] as input high
Pulse duration, GPn[m] as input low
2C ^{(1) (2)}
ns
2C ^{(1) (2)}
ns
(1) The pulse width given is sufficient to generate a CPU interrupt or an EDMA event. However, if a user wants to have the device
recognize the GPIx changes through software polling of the GPIO register, the GPIx duration must be extended to allow the device
enough time to access the GPIO register through the internal bus.
(2) C=SYSCLK4 period in ns.
Table 6-11. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 6-10)
No.
PARAMETER
MIN
MAX
UNIT
3 t_w(GPOH)
4 t_w(GPOL)
Pulse duration, GPn[m] as output high
Pulse duration, GPn[m] as output low
2C ^{(1) (2)}
ns
2C ^{(1) (2)}
ns
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
(2) C=SYSCLK4 period in ns.
GPn[m] as input
GPn[m] as output
2
1
4
3
Figure 6-10. GPIO Port Timing
6.9.3 GPIO Peripheral External Interrupts Electrical Data/Timing
Table 6-12. Timing Requirements for External Interrupts⁽¹⁾ (see Figure 6-11)
No.
PARAMETER
MIN
MAX
UNIT
1 t_w(ILOW)
2 t_w(IHIGH)
Width of the external interrupt pulse low
Width of the external interrupt pulse high
2C ^{(1) (2)}
ns
2C ^{(1) (2)}
ns
(1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have device recognize the
GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow the device enough time to
access the GPIO register through the internal bus.
(2) C=SYSCLK4 period in ns.
GPn[m] as input
2
1
Figure 6-11. GPIO External Interrupt Timing
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Peripheral Information and Electrical Specifications
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