AM1705_1004 Datasheet, PDF(85/155 Page) Texas Instruments

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AM1705_1004 Datasheet, PDF (85/155 Pages) Texas Instruments – AM1705 ARM Microprocessor

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AM1705

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SPRS657A â FEBRUARY 2010 â REVISED APRIL 2010

6.17.1 McASP Peripheral Registers Description(s)

Registers for the McASP are summarized in Table 6-41. The registers are accessed through the

peripheral configuration port. The receive buffer registers (RBUF) and transmit buffer registers (XBUF) can

also be accessed through the DMA port, as listed in Table 6-42

Registers for the McASP Audio FIFO (AFIFO) are summarized in Table 6-43. Note that the AFIFO Write

FIFO (WFIFO) and Read FIFO (RFIFO) have independent control and status registers. The AFIFO control

registers are accessed through the peripheral configuration port.

Table 6-41. McASP Registers Accessed Through Peripheral Configuration Port

McASP0

BYTE

ADDRESS

McASP1

BYTE

ADDRESS

ACRONYM

0x01D0 0000 0x01D0 4000

REV

Revision identification register

0x01D0 0010 0x01D0 4010 PFUNC Pin function register

0x01D0 0014 0x01D0 4014

PDIR

Pin direction register

0x01D0 0018 0x01D0 4018 PDOUT Pin data output register

0x01D0 001C 0x01D0 401C

PDIN

Read returns: Pin data input register

0x01D0 001C 0x01D0 401C PDSET Writes affect: Pin data set register (alternate write address: PDOUT)

0x01D0 0020 0x01D0 4020 PDCLR Pin data clear register (alternate write address: PDOUT)

0x01D0 0044 0x01D0 4044 GBLCTL Global control register

0x01D0 0048 0x01D0 4048 AMUTE Audio mute control register

0x01D0 004C 0x01D0 404C DLBCTL Digital loopback control register

0x01D0 0050 0x01D0 4050 DITCTL DIT mode control register

0x01D0 0060 0x01D0 4060 RGBLCTL Receiver global control register: Alias of GBLCTL, only receive bits are affected - allows

receiver to be reset independently from transmitter

0x01D0 0064 0x01D0 4064 RMASK Receive format unit bit mask register

0x01D0 0068 0x01D0 4068

RFMT

Receive bit stream format register

0x01D0 006C 0x01D0 406C AFSRCTL Receive frame sync control register

0x01D0 0070 0x01D0 4070 ACLKRCTL Receive clock control register

0x01D0 0074 0x01D0 4074 AHCLKRCTL Receive high-frequency clock control register

0x01D0 0078 0x01D0 4078

RTDM Receive TDM time slot 0-31 register

0x01D0 007C 0x01D0 407C RINTCTL Receiver interrupt control register

0x01D0 0080 0x01D0 4080 RSTAT Receiver status register

0x01D0 0084 0x01D0 4084 RSLOT Current receive TDM time slot register

0x01D0 0088 0x01D0 4088 RCLKCHK Receive clock check control register

0x01D0 008C 0x01D0 408C REVTCTL Receiver DMA event control register

0x01D0 00A0 0x01D0 40A0 XGBLCTL Transmitter global control register. Alias of GBLCTL, only transmit bits are affected - allows

transmitter to be reset independently from receiver

0x01D0 00A4 0x01D0 40A4 XMASK Transmit format unit bit mask register

0x01D0 00A8 0x01D0 40A8

XFMT

Transmit bit stream format register

0x01D0 00AC 0x01D0 40AC AFSXCTL Transmit frame sync control register

0x01D0 00B0 0x01D0 40B0 ACLKXCTL Transmit clock control register

0x01D0 00B4 0x01D0 40B4 AHCLKXCTL Transmit high-frequency clock control register

0x01D0 00B8 0x01D0 40B8

XTDM

Transmit TDM time slot 0-31 register

0x01D0 00BC 0x01D0 40BC XINTCTL Transmitter interrupt control register

0x01D0 00C0 0x01D0 40C0 XSTAT Transmitter status register

0x01D0 00C4 0x01D0 40C4 XSLOT Current transmit TDM time slot register

0x01D0 00C8 0x01D0 40C8 XCLKCHK Transmit clock check control register

0x01D0 00CC 0x01D0 40CC XEVTCTL Transmitter DMA event control register

0x01D0 0100 0x01D0 4100 DITCSRA0 Left (even TDM time slot) channel status register (DIT mode) 0

Peripheral Information and Electrical Specifications

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