TMS320DM6467_10 Datasheet, PDF (91/357 Pages) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6467
Digital Media System-on-Chip
SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009
4.3.2 Clock Control
This section describes the following registers: the VPIF (Video)/TSIF clock control and clock disable
registers and the Clock and Oscillator control register.
4.3.2.1 Video Clock Control Register
The Video Clock Control (VIDCLKCTL) register allows the user to select/control the clock muxing for the
video channels' (i.e., channels 1, 2, and 3) output clock source.
31
16
RESERVED
R-0000 0000 0000 0000
15
14
12
11
10
8
7
5
4
3
0
RSV
VCH3CLK
RSV
VCH2CLK
R-0
R/W-111
R-0
R/W-110
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
RESERVED
R-000
VCH1CLK
R/W-1
RESERVED
R-0000
Figure 4-2. VIDCLKCTL Register [0x01C4 0038]
BIT
31:15
14:12
11
10:8
7:5
4
3:0
Table 4-4. VIDCLKCTL Register Bit Descriptions
NAME
RESERVED
VCH3CLK
RSV
VCH2CLK
RESERVED
VCH1CLK
RESERVED
DESCRIPTION
Reserved. Read returns "0".
Video Channel 3 Clock Source.
This field selects the clock source for the Channel 3 output source clock.
000 = CRG0_VCXI (external pin)
001 = CRG1_VCXI (external pin)
010 = SYSCLK8 (PLLC1)
011 = AUXCLK (PLLC1)
100 = VP_CLKIN0 (external pin)
101 = STC_CLKIN (external pin)
110 = VP_CLKIN2 (external pin)
111 = VP_CLKIN3 (external pin)
Reserved. Read returns "0".
Video Channel 2 Clock Source.
This field selects the clock source for the Channel 2 output source clock.
000 = CRG0_VCXI (external pin)
001 = CRG1_VCXI (external pin)
010 = SYSCLK8 (PLLC1)
011 = AUXCLK (PLLC1)
100 = VP_CLKIN0 (external pin)
101 = STC_CLKIN (external pin)
110 = VP_CLKIN2 (external pin)
111 = Reserved
Reserved. Read returns "0".
Video Channel 1 Clock Source.
This bit selects the clock source for the Channel 1 input clock.
0 = VP_CLKIN0 (external pin)
1 = VP_CLKIN1 (external pin)
Reserved. Read returns "0".
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Device Configurations
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