TMS320DM6467_10 Datasheet, PDF (8/357 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
Digital Media System-on-Chip
SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009
www.ti.com
SEE
ADDITIONS/MODIFICATIONS/DELETIONS
Section 7.10.2
DDR2 Interface
Figure 7-27, DM6467 32-Bit DDR2 High Level Schematic:
• Updated/Changed the ± resistor tolerance value to "5%' for the DDR_ZN and DDR_ZP signals
Figure 7-28, DM6467 16-Bit DDR2 High Level Schematic:
• Updated/Changed the ± resistor tolerance value to "5%' for the DDR_ZN and DDR_ZP signals
Section 7.11.4
Table 7-47, Timing Requirements for VPIF VP_CLKINx Inputs:
VPIF Electrical Data/Timing _{• Updated/Changed Cycle time, VP_CLKIN for 0, 1, 2, and 3 into one row}
• Split -729 device into separate column
Table 7-48, Timing Requirements for VPIF Channels 0/1 Video Capture Data and Control Inputs:
• Split -729 device into separate column
Table 7-49, Switching Characteristics Over Recommended Operating Conditions for Video Data Shown With
Respect to VP_CLKO2/3:
• Split -729 device into separate column
Section 7.23.3
SPI Electrical Data/Timing
Master Mode — Additional:
Table 7-118, Additional Output Switching Characteristics of 4-Pin Chip-Select Option in Master Mode:
• Updated/Changed references of "VBUSPER" to "P"
• Added associated "P = " footnote
Table 7-119, Additional Output Switching Characteristics of 5-Pin Option in Master Mode:
• Updated/Changed all references of "VBUSPER" to "P"
Section 7.29.1
• Updated/Changed "The JTAG ID register is a read-only ..." paragraph [Cleared Documentation
JTAG ID (JTAGID) Register
Feedback Issue]
Description(s)
Figure 7-96, JTAG ID Register Description - DM6467 Register Value - 0xXB77 002F:
• Updated/Changed the VARIANT Reset value to "000X"; Silicon Revision specific [Cleared
Documentation Feedback Issue]
Table 7-150, JTAG ID Register Selection Bit Descriptions:
• Updated/Changed the "Variant (4-Bit) value. DM6467 value:" description; Silicon Revision specific
[Cleared Documentation Feedback Issue]
8
Revision History
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