TMS320DM6467_10 Datasheet, PDF (40/357 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
Digital Media System-on-Chip
SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009
www.ti.com
Table 3-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued)
SIGNAL
NAME
PCI_STOP/
HCNTL0/
EM_WE
PCI_CBE2/
HDS2/
EM_CS2
PCI_CBE3/
HR/W
EM_CS3
PCI_AD15/
HD15/EM_D15
PCI_AD14/
HD14 /EM_D14
PCI_AD13/
HD13/EM_D13
PCI_AD12/
HD12/EM_D12
PCI_AD11/
HD11/EM_D11
PCI_AD10/
HD10/EM_D10
PCI_AD9/
HD9/EM_D9
PCI_AD8/
HD8/EM_D8
PCI_AD7/
HD7/EM_D7
PCI_AD6/
HD6/EM_D6
PCI_AD5/
HD5/EM_D5
PCI_AD4/
HD4/EM_D4
PCI_AD3/
HD3/EM_D3
PCI_AD2/
HD2/EM_D2
PCI_AD1/
HD1/EM_D1
PCI_AD0/
HD0/EM_D0
TYPE⁽¹⁾ OTHER^{(2) (3)}
NO.
DESCRIPTION
D5 I/O/Z
C4 I/O/Z
A5 I/O/Z
E5 I/O/Z
C1 I/O/Z
E4 I/O/Z
D3 I/O/Z
E3 I/O/Z
D2 I/O/Z
F5 I/O/Z
D1 I/O/Z
E2 I/O/Z
F3 I/O/Z
E1 I/O/Z
G5 I/O/Z
F2 I/O/Z
G4 I/O/Z
F1 I/O/Z
G3 I/O/Z
IPU
DV_DD33
IPU
DV_DD33
IPU
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is the write enable output EM_WE (O/Z).
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is Chip Select 2 output EM_CS2 (O/Z). This is the chip
select used for EMIFA boot modes. Asynchronous memories (i.e., NOR Flash) or
NAND flash.
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is Chip Select 3 output EM_CS3 (O/Z). Asynchronous
memories (i.e., NOR Flash).
These pins are multiplexed between PCI, HPI, and EMIFA.
For EMIFA mode, these pins are the 16-bit bidirectional data bus (EM_D[15:0])
[I/O/Z].
When EMIFA is configured for an 8-bit asynchronous memory, only EM_D[7:0]
pins are used.
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