TMS320DM6467_10 Datasheet, PDF (321/357 Pages) Texas Instruments – Digital Media System-on-Chip

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TMS320DM6467
Digital Media System-on-Chip
SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009
Master Mode — Additional
Table 7-116. Additional Output Switching Characteristics of 4-Pin Enable Option in Master Mode⁽¹⁾⁽²⁾
NO.
17
t_d(EN-CLK)
PARAMETER
Delay time, slave assertion of SPI_EN active to first SPI_CLK
rising edge from master, 4-pin mode, polarity = 0, phase = 0
Delay time, slave assertion of SPI_EN active to first SPI_CLK
rising edge from master, 4-pin mode, polarity = 0, phase = 1
Delay time, slave assertion of SPI_EN active to first SPI_CLK
falling edge from master, 4-pin mode, polarity = 1, phase = 0
Delay time, slave assertion of SPI_EN active to first SPI_CLK
falling edge from master, 4-pin mode, polarity = 1, phase = 1
MIN
MAX UNIT
3P + 6
0.5T + 3P + 6
ns
3P + 6
0.5T + 3P + 6
(1) T = period of SPI_CLK; P = period of SPI core clock
(2) Figure 7-87 shows only polarity = 0, phase = 0 as an example. In this case, the Master SPI is ready with new data before SPI_EN
assertion.
Table 7-117. Additional Input Timing Requirements of 4-Pin Enable Option in Master Mode⁽¹⁾⁽²⁾
NO.
18
t_d(CLK-EN)
Delay time, max delay for slave to deassert SPI_EN after final
SPI_CLK falling edge, 4-pin mode,
polarity = 0, phase = 0
Delay time, max delay for slave to deassert SPI_EN after final
SPI_CLK falling edge, 4-pin mode,
polarity = 0, phase = 1
Delay time, max delay for slave to deassert SPI_EN after final
SPI_CLK rising edge, 4-pin mode,
polarity = 1, phase = 0
Delay time, max delay for slave to deassert SPI_EN after final
SPI_CLK rising edge, 4-pin mode,
polarity = 1, phase = 1
MIN
MAX UNIT
0.5T + P
P
ns
0.5T + P
P
(1) T = period of SPI_CLK; P = period of SPI core clock
(2) Figure 7-87 shows only polarity = 0, phase = 0 as an example. In this case, the Master SPI is ready with new data before SPI_EN
deassertion.
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Peripheral Information and Electrical Specifications 321