TMS320DM6467_10 Datasheet, PDF (224/357 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
Digital Media System-on-Chip
SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009
VIDCLKCTL.VCH1CLK
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VP_CLKIN1
VP_CLKIN0
VP_CLKIN1
1
VP_CLKIN0
0
VPIF
Channel 1
Input Clock Source
VSCLKDIS.VID1
Figure 7-36. VPIF Capture Channel 1 Source Clock Selection
For both the dual 8-bit or 16-bit display modes, the VPIF Display Channel 2 outputs data synchronous to
VP_CLKO2. The source clock for the VP_CLKO2 output is selectable from a number of external clock
inputs or on-chip clock sources (see Figure 7-37).
VIDCLKCTL.VCH2CLK
VP_CLKIN2
VP_CLKIN2
GP[4]/STC_CLKIN
STC_CLKIN
VP_CLKIN0
VP_CLKIN0
DEV_MXI/DEV_CLKIN
(27 MHz)
PLL
Controller 1
AUXCLK
SYSCLK8^(B)
111^(A)
110
101
100
011
010
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
CRG1_VCXI
001
URXD2/CRG1_VCXI/GP[39]/CRG0_VCXI
UCTS2/USD2/CRG0_VCXI/GP[42]/TS1_PTSO
11x CRG0_VCXI
000
10x
PINMUX0.CRGMUX
VPIF
Channel 2
Output Clock Source
VSCLKDIS.VID2
(A) 111 = Reserved.
(B) For the -729 devices, use an external clock source for the 54-/74.25-/108-MHz VPIF clock.
Figure 7-37. VPIF Display Channel 2 Source Clock Selection
For the dual 8-bit display mode, the VPIF Display Channel 3 outputs data synchronous to VP_CLKO3.
The source clock for the VP_CLKO3 output is selectable from a number of external clock inputs or on-chip
clock sources (see Figure 7-38). When the 16-bit display mode for Channel 3 is selected, the clock source
must match that of Channel 2 (VIDCLKCTL.VCH3CLK = VCH2CLK).
224 Peripheral Information and Electrical Specifications
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