TMS320DM6467_10 Datasheet, PDF (332/357 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
Digital Media System-on-Chip
SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009
www.ti.com
7.24.2 UART Peripheral Register Description(s)
Table 7-126 shows the UART register name summary. Table 7-127, Table 7-128, and Table 7-129 show
the UART0/1/2 registers, respectively along with their configuration requirements.
ACRONYM
RHR
THR
IER
IIR
FCR
LCR
MCR
LSR
MSR
SPR
TCR
TLR
MDR1
MDR2
SFLSR
RESUME
SFREGL
SFREGH
TXFLL
TXFLH
RXFLL
Table 7-126. UART Register Summary
REGISTER NAME
Receive Holding Register
Transmit Holding Register
Interrupt Enable Register
Interrupt Identification Register
FIFO Control Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratchpad Register
Transmission Control Register
Trigger Level Register
Mode Definition Register 1
Mode Definition Register 2
Status FIFO Line Status Register
Resume Register
Status FIFO Register Low
Status FIFO Register High
Transmit Frame Length Low Register
Transmit Frame Length High Register
Receive Frame Length Low Register
ACRONYM
RXFLH
BLR
ACREG
SCR
SSR
EBLR
MVR
SYSC
SYSS
WER
CFPS
DLL
DLH
UASR
EFR
XON1
XON2
XOFF1
XOFF2
ADDR1
ADDR2
REGISTER NAME
Receive Frame Length High Register
BOF Control Register
Auxilliary Control Register
Supplementary Control Register
Supplementary Status Register
BOF Length Register
Module Version Register
System Configuration Register
System Status Register
Wake-up Enable Register
Carrier Frequency Prescaler Register
Divisor Latch Low Register
Divisor Latch High Register
UART Autobauding Status Register
Enhanced Feature Register
UART XON1 Character Register
UART XON2 Character Register
UART XOFF1 Character Register
UART XOFF2 Character Register
IrDA Address 1 Register
IrDA Address 2 Register
332 Peripheral Information and Electrical Specifications
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