TMS320DM6467_10 Datasheet, PDF (256/357 Pages) Texas Instruments – Digital Media System-on-Chip

TMS320DM6467
Digital Media System-on-Chip
SPRS403F – DECEMBER 2007 – REVISED OCTOBER 2009
7.16.3 EMAC Peripheral Register Description(s)
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HEX ADDRESS RANGE
0x01C8 0000
0x01C8 0004
0x01C8 0008
0x01C8 000C - 0x01C8 000F
0x01C8 0010
0x01C8 0014
0x01C8 0018
0x01C8 001C - 0x01C8 007F
0x01C8 0080
0x01C8 0084
0x01C8 0088
0x01C8 008C
0x01C8 0090
0x01C8 0094
0x01C8 0098 - 0x01C8 009F
0x01C8 00A0
0x01C8 00A4
0x01C8 00A8
0x01C8 00AC
0x01C8 00B0
0x01C8 00B4
0x01C8 00B8
0x01C8 00BC
0x01C8 00C0 - 0x01C8 00FF
0x01C8 0100
0x01C8 0104
0x01C8 0108
0x01C8 010C
0x01C8 0110
0x01C8 0114
0x01C8 0118 - 0x01C8 011F
0x01C8 0120
0x01C8 0124
0x01C8 0128
0x01C8 012C
0x01C8 0130
0x01C8 0134
0x01C8 0138
0x01C8 013C
0x01C8 0140
0x01C8 0144
0x01C8 0148
0x01C8 014C
0x01C8 0150
0x01C8 0154
Table 7-69. Ethernet MAC (EMAC) Control Registers
ACRONYM
TXIDVER
TXCONTROL
TXTEARDOWN
–
RXIDVER
RXCONTROL
RXTEARDOWN
–
TXINTSTATRAW
TXINTSTATMASKED
TXINTMASKSET
TXINTMASKCLEAR
MACINVECTOR
MACEOIVECTOR
–
RXINTSTATRAW
RXINTSTATMASKED
RXINTMASKSET
RXINTMASKCLEAR
MACINTSTATRAW
MACINTSTATMASKED
MACINTMASKSET
MACINTMASKCLEAR
–
RXMBPENABLE
RXUNICASTSET
RXUNICASTCLEAR
RXMAXLEN
RXBUFFEROFFSET
RXFILTERLOWTHRESH
–
RX0FLOWTHRESH
RX1FLOWTHRESH
RX2FLOWTHRESH
RX3FLOWTHRESH
RX4FLOWTHRESH
RX5FLOWTHRESH
RX6FLOWTHRESH
RX7FLOWTHRESH
RX0FREEBUFFER
RX1FREEBUFFER
RX2FREEBUFFER
RX3FREEBUFFER
RX4FREEBUFFER
RX5FREEBUFFER
REGISTER NAME
Transmit identification and version register
Transmit control register
Transmit teardown register
Reserved
Receive identification and version register
Receive control register
Receive teardown register
Reserved
Transmit interrupt status (unmasked) register
Transmit interrupt status (masked) register
Transmit interrupt mask set register
Transmit interrupt mask clear register
MAC input vector register
MAC end of interrupt vector register
Reserved
Receive interrupt status (unmasked) register
Receive interrupt status (masked) register
Receive interrupt mask set register
Receive interrupt mask clear register
MAC interrupt status (unmasked) register
MAC interrupt status (masked) register
MAC interrupt mask set register
MAC interrupt mask clear register
Reserved
Receive multicast/broadcast/promiscuous channel enable register
Receive unicast enable set register
Receive unicast clear register
Receive maximum length register
Receive buffer offset register
Receive filter low priority frame threshold register
Reserved
Receive channel 0 flow control threshold register
Receive channel 1 flow control threshold register
Receive channel 2 flow control threshold register
Receive channel 3 flow control threshold register
Receive channel 4 flow control threshold register
Receive channel 5 flow control threshold register
Receive channel 6 flow control threshold register
Receive channel 7 flow control threshold register
Receive channel 0 free buffer count register
Receive channel 1 free buffer count register
Receive channel 2 free buffer count register
Receive channel 3 free buffer count register
Receive channel 4 free buffer count register
Receive channel 5 free buffer count register
256 Peripheral Information and Electrical Specifications
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