OMAP5912 Datasheet, PDF (85/254 Pages) Texas Instruments – Applications Processor

Introduction
Table 2−5. Signal Descriptions (Continued)
SIGNAL
LCD.AC
ZDY
BALL#
ZZG
BALL#
F10
B15
LCD.BLUE0
LCD.HS
LCD.PCLK
L17
N19
D15
C20
A14
C15
LCD.P[15:0]
LCD.RED0
LCD.VS
C12 D12
E11 A13
B14 A15
F11 C13
D13 A16
C15 E12
D14 C16
B16 A17
K14
B15
D15 C16
A17 G13
B17 C17
D16 D17
C18 B19
A20 H13
G14 C19
B21 D18
N21
B18
† _{I = Input, O = Output, Z = High-Impedance}
DESCRIPTION
LCD AND LCDCONV INTERFACE
LCD AC-bias. LCD.AC signals the LCD display to switch the polarity of the
row and column power supplies to counteract charge buildup causing DC
offset. In TFT mode, LCD.AC is used as the output enable to latch LCD pixel
data using the pixel clock.
Blue bit 0 in 18-bit LCD output mode
LCD horizontal sync. LCD_HSYNC is the line clock that signals the end of a
line of pixels to the LCD display panel. In TFT mode, LCD_HSYNC is the
horizontal synchronization signal.
LCD pixel clock output. Clock output provided to synchronize pixel data to
LCD display panels. In passive mode, LCD_PCLK transitions only when
LCD.P[15:0] is valid. In active mode, LCD_PCLK transitions continuously
and LCD.AC is used as the output enable when LCD.P[15:0] is valid.
LCD pixel data bits
Red bit 0 in 18-bit LCD output mode
LCD vertical synchronization (sync) output. LCD.VS is the frame clock that
signals the start of a new frame of pixels to the LCD display panel. In TFT
mode, LCD.VS is the vertical synchronization signal.
TYPE^†
O
O
O
O
O
O
O
December 2003 − Revised March 2005
SPRS231D
85