OMAP5912 Datasheet, PDF (61/254 Pages) Texas Instruments – Applications Processor

Introduction
Table 2−4. ZZG Package Terminal Characteristics (Continued)
ZZG
BALL
NO.
SIGNAL NAME
TYPE^†
PULLUP/
MUX CTRL SETTING _PULLDN‡
BUFFER
STRENGTH^§
OTHER^¶
RESET
STATE^#
SUPPLY
F18
KB.C[0]
MPUIO0
O
Reg3[17:15] = 000
PU20,
2 mA (Lv)
A, F
I/O
Reg3[17:15] = 001
PD20
3 mA (Hv)
0
DV_DD1
E19
KB.R[4]
MPUIO15
I
Reg3[20:18] = 000 PU100,
2 mA (Lv)
A, F
I/O
Reg3[20:18] = 001
PD20
3 mA (Hv)
Z
DV_DD1
E20
KB.R[3]
MPUIO13
I
Reg3[23:21] = 000 PU100,
2 mA (Lv)
A, F
I/O
Reg3[23:21] = 001
PD20
3 mA (Hv)
Z
DV_DD1
H14
KB.R[2]
MPUIO10
I
Reg3[26:24] = 000 PU100,
2 mA (Lv)
A, F
I/O
Reg3[26:24] = 001
PD20
3 mA (Hv)
Z
DV_DD1
F19
KB.R[1]
MPUIO9
I
Reg3[29:27] = 000 PU100,
2 mA (Lv)
A, F
I/O
Reg3[29:27] = 001
PD20
3 mA (Hv)
Z
DV_DD1
G18
KB.R[0]
MPUIO8
I
Reg4[2:0] = 000
PU100,
2 mA (Lv)
A, F
I/O
Reg4[2:0] = 001
PD20
3 mA (Hv)
Z
DV_DD1
G19
KB.C[5]
GPIO28
O
Reg3[2:0] = 000
PU20,
2 mA (Lv)
A, F
I/O
Reg3[2:0] = 111
PD20
3 mA (Hv)
0
DV_DD1
G20
MCBSP1.CLKS
GPIO62
I
Reg4[8:6] = 000
PU20,
2 mA (Lv)
A, F
I/O
Reg4[8:6] = 111
PD20
3 mA (Hv)
−
DV_DD1
G21
MCBSP1.CLKX
GPIO54
I/O
Reg4[11:9] = 000
PU20,
2 mA (Lv) A, F, G1
Z
I/O
Reg4[11:9] = 111
PD20
3 mA (Hv)
DV_DD1
H15
MCBSP1.FSX
MCBSP1.DX
I/O
Reg4[14:12] = 000
PU20,
2 mA (Lv) A, F, G1
Z
O
Reg4[14:12] = 001
PD20
3 mA (Hv)
DV_DD1
MCBSP1.DXZ
O/Z
Reg4[14:12] = 010
GPIO53
I/O
Reg4[14:12] = 111
H18
MCBSP1.DX
MCBSP1.ESX
O
Reg4[17:15] = 000
PU20,
2 mA (Lv) A, F, G1
0
I/O
Reg4[17:15] = 001
PD20
3 mA (Hv)
DV_DD1
MCBSP1.DXZ
O/Z
Reg4[17:15] = 010
GPIO52
I/O
Reg4[17:15] = 111
H20
MCBSP1.DR
GPIO51
I
Reg4[20:18] = 000
PU20,
2 mA (Lv)
A, F
I/O
Reg4[20:18] = 111
PD20
3 mA (Hv)
LZ
DV_DD1
† _{I = Input, O = Output, Z = High-Impedance}
‡ _{PD20 = 20-µA internal pulldown, PD100=100-µA internal pulldown, PU20 = 20-µA internal pullup, PU100 = 100-µA internal pullup. Pullup or}
pulldown can be enabled or disabled by software.
§ _{Lv = Low voltage (1.65 V), Hv = High voltage (2.5 V)}
¶ _{A = Standard LVCMOS input/output}
G1 = Terminal may be gated by BFAIL
B = SUBLVDS input/ouput
G2 = Terminal may be gated by GPIO9 and MPUIO3
C = USB transceiver input/ouput
G3 = Terminal my be gated by BFAIL and OMAP5912 Internal Reset
D = I²C input/output buffers
H1 = Terminal may be 3-stated by BFAIL input
E = Analog oscillator terminals
H3 = MCSI1.DOUT pin can be forced into a high-impedance
F = Boundary-scannable terminal
state by the OMAP5912 HIGH_IMP3 control bit
K = Output buffer includes a serial resistor of 20 Ω to match with PCB line impedance and ensure proper signal integrity
# _{Z = High-Impedance, LZ = Low-Impedance (pin is driven), 1 = Output driven high, 0 = Output driven low}
NOTES: 3. NA denotes no multiplexing on the ball
4. ‘Regx’ denotes the terminal multiplexing register that controls the specified terminal where Regx = FUNC_MUX_CTRL_x
December 2003 − Revised March 2005
SPRS231D
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