OMAP5912 Datasheet, PDF (153/254 Pages) Texas Instruments – Applications Processor

Functional Overview
BYTE
ADDRESS
FFFE:CC08
FFFE:CC20
FFFE:CC24
FFFE:CC3C
FFFE:CC64
FFFE:CC68
FFFE:CC70
FFFE:CC74
FFFE:CC78
FFFE:CC80
FFFE:CC84
FFFE:CC8C
FFFE:CC90
FFFE:CC94
FFFE:CC98
FFFE:CC9C
FFFE:CCC0
FFFE:CCC4
FFFE:CCC8
FFFE:CCCC
FFFE:CCBC
Table 3−62. Traffic Controller EMIFF Registers
REGISTER NAME
DESCRIPTION
ACCESS ACCESS
WIDTH TYPE
RESET
VALUE
EMIFF_PRIO_REG
EMIFF Priority Register
32
R/W 0000 0000h
EMIFF_SDRAM_CONFIG
EMIFF SDRAM Configuration Register
32
R/W 0061 8800h
EMIFF_MRS
EMIFF SDRAM MRS Register
32
R/W 0000 0037h
EMIFF_SDRAM_CONFIG_2
EMIFF SDRAM Configuration Register 2
32
R/W 0000 0003h
DLL_WRT_CTL
DLL WRT Control Register (write byte)
32
R/W 0000 0000h
DLL_WRT_STAT
DLL WRT Status Register (read lower byte)
32
R
0000 0000h
EMIFF_MRS_NEW
EMIFF SDRAM MRS Register (duplicate)
32
R/W 0000 0037h
EMIFF_EMRS0
EMIFF SDRAM EMRS 0 Register
32
R/W 0000 0000h
EMIFF_EMRS1
EMIFF SDRAM EMRS 1 Register
32
R/W 0000 0000h
EMIFF_OP
EMIFF SDRAM Operation Register
32
R/W 0000 0004h
EMIFF_MCMD
EMIFF SDRAM Manual Command Register
32
R/W 0000 0000h
EMIFF_TIMEOUT1
EMIFF Dynamic Arb. Priority Timeout 1
Register
32
R/W 0000 0000h
EMIFF_TIMEOUT2
EMIFF Dynamic Arb. Priority Timeout 2
Register
32
R/W 0000 0000h
EMIFF_TIMEOUT3
EMIFF Dynamic Arb. Priority Timeout 3
Register
32
R/W 0000 0000h
EMIFF_ABORT_ADDR
EMIFF Abort Address Register
32
R
0000 0000h
EMIFF_ABORT_TYPE
EMIFF Abort Type Register
32
R
0000 0000h
DLL_URD_CTL
DLL URD Control Register (read upper byte)
32
R/W 0000 0000h
DLL_URD_STAT
DLL URD Status Register (read upper byte)
32
R
0000 0000h
EMIFF_EMRS2
EMIFF SDRAM EMRS 2 Register
32
R/W 0000 0000h
DLL_LRD_CTL
DLL LRD Control Register (read lower byte)
32
R/W 0000 0000h
DLL_LRD_STAT
DLL LRD Status Register (read lower byte)
32
R
0000 0000h
Table 3−63. MPU Clock/Reset/Power Mode Control Registers
BYTE
ADDRESS
REGISTER NAME
DESCRIPTION
ACCESS ACCESS
WIDTH TYPE
FFFE:CE00 ARM_CKCTL
MPU Clock Control Register
32
R/W
FFFE:CE04 ARM_IDLECT1
MPU Idle Control 1 Register
32
R/W
FFFE:CE08 ARM_IDLECT2
MPU Idle Control 2 Register
32
R/W
FFFE:CE0C ARM_EWUPCT
MPU External Wakeup Control Register
32
R/W
FFFE:CE10 ARM_RSTCT1
MPU Reset Control 1 Register
32
R/W
FFFE:CE14 ARM_RSTCT2
MPU Reset Control 2 Register
32
R/W
FFFE:CE18 ARM_SYSST
MPU System Status Register
32
R/W
FFFE:CE1C ARM_CKOUT1
MPU Clock Out Definition Register 1
32
R/W
FFFE:CE20 ARM_CKOUT2
MPU Clock Out Definition Register 2
32
R/W
FFFE:CE24 ARM_IDLECT3
MPU Idle Enable Control Register 3
32
R/W
RESET
VALUE
3000h
0400h
0100h
003Fh
0000h
0000h
0038h
0015h
0000h
0015h
December 2003 − Revised March 2005
SPRS231D 153