OMAP5912 Datasheet, PDF (238/254 Pages) Texas Instruments – Applications Processor

Electrical Specifications
5.16 Inter-Integrated Circuit (I²C) Timing
Table 5−35 assumes testing over recommended operating conditions (see Figure 5−50).
Table 5−35. I²C Signals (I2C.SDA and I2C.SCL) Switching Characteristics
NO.
PARAMETER
IC1 t_c(SCL)
Cycle time, I2C.SCL
Setup time, I2C.SCL high before I2C.SDA low (for a repeated
IC2 t_{su(SCLH-SDAL) START condition)}
STANDARD
MODE
MIN MAX
10^†
4.7
FAST
MODE
MIN MAX
2.5
UNIT
µs
0.6
µs
IC3 t_h(SCLL-SDAL)
Hold time, I2C.SCL low after I2C.SDA low (for a repeated START
condition)
4
0.6
µs
IC4 t_w(SCLL)
Pulse duration, I2C.SCL low
4.7
1.3
µs
IC5 t_w(SCLH)
Pulse duration, I2C.SCL high
IC6 t_su(SDA-SDLH) Setup time, I2C.SDA valid before I2C.SCL high
4
0.6
µs
250
‡ ₁₀₀
ns
IC7 t_h(SDA-SDLL) Hold time, I2C.SDA valid after I2C.SCL low (for I²C bus devices)
0
0
0.9 µs
IC8 t_w(SDAH)
Pulse duration, I2C.SDA high between STOP and START conditions 4.7
1.3
µs
IC9 t_r(SDA)
IC10 t_r(SCL)
Rise time, I2C.SDA
Rise time, I2C.SCL
1000^§
1000^§
300^§ ns
300^§ ns
IC11 t_f(SDA)
Fall time, I2C.SDA
300^§
300^§ ns
IC12 t_f(SCL)
Fall time, I2C.SCL
300^§
300^§ ns
IC13 t_{su(SCLH-SDAH)} Setup time, I2C.SCL high before I2C.SDA high (for STOP condition)
4.0
0.6
µs
IC14 t_w(SP)
IC15 C_b¶
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
0
50 ns
400
400 pF
† _{In the master-only I}2_{C operating mode of OMAP5912, minimum cycle time for I2C.SCL is 12 µs.}
‡ _{The maximum th(SCLL-SDAL) has only to be met if the device does not stretch the low period (tw(SCLL)) of the I2C.SCL signal.}
§ _{Max of fall and rise times were measured while considering an internal pullup value of 520 Ω.}
¶ _{Cb = The total capacitance of one bus line in pF.}
I2C.SDA
I2C.SCL
IC8
IC4
IC10
IC6
IC5
IC1
IC3
IC12
IC7
IC14
IC13
IC3
IC2
Stop Start
Repeated
Start
Stop
NOTES: A. A device must internally provide a hold time of at least 300 ns for the I2C.SDA signal (referred to the V_IHmin of the I2C.SCL signal)
to bridge the undefined region of the falling edge of I2C.SCL.
B. The maximum t_{h(SCLL−SDAL)} has only to be met if the device does not stretch the LOW period (t_w(SCLL)) of the I2C.SCL signal.
C. A Fast-mode I²C-bus device can be used in a Standard-mode I²C-bus system, but the requirement t_{su(SDA−SDLH)} • 250 ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the I2C.SCL signal. If such a device
does stretch the LOW period of the I2C.SCL signal, it must output the next data bit to the I2C.SDA line t_r max + t_{su(SDA−SDLH)} =
1000 + 250 = 1250 ns (according to the standard-mode I²C-bus specification) before the I2C.SCL line is released.
D. C_b = total capacitance of one bus line in pF. If mixed with fast-mode devices, faster fall times are allowed.
Figure 5−50. I²C Timings
238 SPRS231D
December 2003 − Revised March 2005