OMAP5912 Datasheet, PDF (132/254 Pages) Texas Instruments – Applications Processor

Functional Overview
DSP WORD
ADDRESS
0x00 9200h
0x00 9202h
0x00 9208h
0x00 920Ah
0x00 920Ch
0x00 920Eh
0x00 9210h
0x00 9212h
0x00 9214h
0x00 9216h
0x00 9218h
0x00 921Ah
0x00 921Ch
0x00 9220h
Table 3−32. General-Purpose Timer3 Registers
MPU BYTE
ADDRESS
REGISTER NAME
DESCRIPTION
ACCESS ACCESS
WIDTH TYPE
RESET
VALUE
FFFB:2400 GPTMR3_TIDR
GPTimer3 Identification Register
16/32
R
0000 0010h
FFFB:2404
Reserved
FFFB:2410 GPTMR3_TIOCP_CFG GPTimer3 OCP Configuration Register 16/32
R/W 0000 0000h
FFFB:2414 GPTMR3_TISTAT
GPTimer3 System Status Register
16/32
R
0000 0000h
FFFB:2418 GPTMR3_TISR
GPTimer3 Status Register
16/32
R/W 0000 0000h
FFFB:241C GPTMR3_TIER
GPTimer3 Interrupt Enable Register
16/32
R/W 0000 0000h
FFFB:2420 GPTMR3_TWER
GPTimer3 Wake Up Enable Register
16/32
R/W 0000 0000h
FFFB:2424 GPTMR3_TCLR
GPTimer3 Control Register
16/32
R/W 0000 0000h
FFFB:2428 GPTMR3_TCRR
GPTimer3 Counter Register
16/32
R/W 0000 0000h
FFFB:242C GPTMR3_TLDR
GPTimer3 Load Register
16/32
R/W 0000 0000h
FFFB:2430 GPTMR3_TTGR
GPTimer3 Trigger Register
16/32
R/W FFFF FFFFh
FFFB:2434 GPTMR3_TWPS
GPTimer3 Write Posted Register
16/32
R
0000 0000h
FFFB:2438 GPTMR3_TMAR
GPTimer3 Match Register
16/32
R/W 0000 0000h
FFFB:2440 GPTMR3_TSICR
GPTimer3 Synchronization Interface
Control Register
16/32
R/W 0000 0004h
DSP WORD
ADDRESS
0x00 9600h
0x00 9602h
0x00 9608h
0x00 960Ah
0x00 960Ch
0x00 960Eh
0x00 9610h
0x00 9612h
0x00 9614h
0x00 9616h
0x00 9618h
0x00 961Ah
0x00 961Ch
0x00 9620h
MPU BYTE
ADDRESS
FFFB:2C00
FFFB:2C04
FFFB:2C10
FFFB:2C14
FFFB:2C18
FFFB:2C1C
FFFB:2C20
FFFB:2C24
FFFB:2C28
FFFB:2C2C
FFFB:2C30
FFFB:2C34
FFFB:2C38
FFFB:2C40
Table 3−33. General-Purpose Timer4 Registers
REGISTER NAME
DESCRIPTION
ACCESS
WIDTH
GPTMR4_TIDR
GPTimer4 Identification Register
16/32
Reserved
GPTMR4_TIOCP_CFG GPTimer4 OCP Configuration Register 16/32
GPTMR4_TISTAT
GPTimer4 System Status Register
16/32
GPTMR4_TISR
GPTimer4 Status Register
16/32
GPTMR4_TIER
GPTimer4 Interrupt Enable Register
16/32
GPTMR4_TWER
GPTimer4 Wake Up Enable Register
16/32
GPTMR4_TCLR
GPTimer4 Control Register
16/32
GPTMR4_TCRR
GPTimer4 Counter Register
16/32
GPTMR4_TLDR
GPTimer4 Load Register
16/32
GPTMR4_TTGR
GPTimer4 Trigger Register
16/32
GPTMR4_TWPS
GPTimer4 Write Posted Register
16/32
GPTMR4_TMAR
GPTimer4 Match Register
16/32
GPTMR4_TSICR
GPTimer4 Synchronization Interface
Control Register
16/32
ACCESS
TYPE
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
RESET
VALUE
0000 0010h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
0000 0000h
FFFF FFFFh
0000 0000h
0000 0000h
0000 0004h
132 SPRS231D
December 2003 − Revised March 2005