OMAP5912 Datasheet, PDF (233/254 Pages) Texas Instruments – Applications Processor

Electrical Specifications
5.13 Parallel Camera Interface Timing
Table 5−31 assumes testing over recommended operating conditions (see Figure 5−43).
Table 5−31. Camera Interface Timing Requirements
NO.
MIN
MAX UNIT
C1 1/[t_c(LCLK)]
Operating frequency, CAM.LCLK
48 MHz
C3 t_w(LCLK)
Pulse duration, CAM.LCLK high or low
0.45P1^† 0.55P1^† ns
C5 t_r(LCLK)
Rise time, CAM.LCLK^‡
0.25P1^† ns
C6 t_f(LCLK)
Fall time, CAM.LCLK^‡
0.25P1^† ns
C9 t_su(LCLKH-DV) Setup time, CAM.D[7:0] data valid before CAM.LCLK high
1^§
ns
C10 t_h(DV-LCLKH) Hold time, CAM.D[7:0] data valid after CAM.LCLK high
6^§
ns
C11 t_su(LCLKH-DV) Setup time, CAM.VS/CAM.HS active before CAM.LCLK high
1^§
ns
C12 t_h(DV-LCLKH) Hold time, CAM.VS/CAM.HS active after CAM.LCLK high
6^§
ns
† _{P1 = Period of CAM.LCLK in nanoseconds (ns).}
‡ _{In this table, the timing values of parameters C5 and C6 (CAM.LCLK) are given by considering the CMOS thresholds: 0.3DVDD to 0.7DVDD. By}
considering t_r and t_f time from 10% to 90% of DV_DD, t_r and t_f = 0.45P1 for parameters C5 and C6.
§ _{The polarity of CAM.LCLK is selectable via the POLCLK bit in the CTRLCLOCK register. Although data is latched on rising CAM.LCLK in the}
timing diagrams, these timing parameters also apply to falling CAM.LCLK when POLCLK = 1.
CAM.LCLK
CAM.VS
CAM.HS
CAM.D[7:0]
C3
C1
C3
C11
C11
C12
C12
C9
U1
C10
Y1
V1
C10
C9
Yn
Figure 5−43. Camera Interface Timing
December 2003 − Revised March 2005
SPRS231D 233