OMAP5912 Datasheet, PDF (224/254 Pages) Texas Instruments – Applications Processor

Electrical Specifications
Table 5−18. McBSP Switching Characteristics^{†‡§} (Continued)
NO.
PARAMETER
MIN MAX UNIT
M7 t_d(CKXH-DXV)
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted
when in data delay 0 (XDATDLY = 00b) mode.
McBSP1
McBSP2
McBSP3
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
−8 10.25
3.5 34.75
−6.75 9.75
ns
2.75 26.75
−9.75 9.75
3
39
M9 t_d(FXH-DXV)
Delay time, FSX high to DX valid^¶
Only applies to first bit transmitted when in data delay 0
(XDATDLY = 00b) mode.
McBSP1
McBSP2
McBSP3
FSX int
FSX ext
FSX int
FSX ext
FSX int
FSX ext
29.5
35.75
19.75
ns
24.25
15
18
† _{Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, the timing references of that signal are also}
inverted.
‡ _{P = 1/(DSPPER_CK or DSPXOR_CK) for McBSP 1 and 3, or 1/(ARMPER_CK clock frequency) in nanoseconds (ns) for McBSP2.}
§ _{T = CLKRX period = (1 + CLKGDV) * P}
C = CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D = CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ _{Only DXENA = 0 is supported for all OMAP5912 McBSPs.}
MCBSP1.CLKS
MCBSPx.CLKR/X
MCBSP2.FSR(internal)
MCBSPx.FSR/X(ext)
MCBSPx.DR(RDATDLY=00b)
MCBSPx.DR(RDATDLY=01b)
MCBSPx.DR(RDATDLY=10b)
M2, M12
M0
M1, M11
M3, M12
M4
M4
M16
M15
M18
M17
Bit (n−1)
Bit (n−2)
Bit (n−3)
M18
M17
Bit (n−1)
Bit (n−2)
M17
M18
Bit (n−1)
Bit (n−4)
Bit (n−3)
Bit (n−2)
NOTE: For McBSP1 and McBSP3, the receiver clock and frame sync inputs are driven by FSX and CLKX via internal loopback connections
enabled via software configuration.
Figure 5−34. McBSP Receive Timing
224 SPRS231D
December 2003 − Revised March 2005