TMS320C6657_15 Datasheet, PDF (83/245 Pages) Texas Instruments – TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor

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TMS320C6655, TMS320C6657
SPRS814B – MARCH 2012 – REVISED APRIL 2015
4.3.12 IPC Generation (IPCGRx) Registers
IPCGRx are the IPC interrupt generation registers to facilitate inter CorePac interrupts.
The C6657 has two IPCGRx registers (IPCGR0 and IPCGR1) while the C6655 has only IPCGR0. These
registers can be used by external hosts or CorePacs to generate interrupts to other CorePacs. A write of 1
to the IPCG field of the IPCGRx register will generate an interrupt pulse to CorePacx (0 <= x <= 1).
These registers also provide a Source ID facility by which up to 28 different sources of interrupts can be
identified. Allocation of source bits to source processor and meaning is entirely based on software
convention. The register field descriptions are given in the following tables. Virtually anything can be a
source for these registers as this is completely controlled by software. Any master that has access to
BOOTCFG module space can write to these registers. The IPC Generation Register is shown in Figure 4-
11 and described in Table 4-13.
Figure 4-11. IPC Generation Registers (IPCGRx)
31
30
29
28
27
8
SRCS SRCS SRCS SRCS
27
26
25
24
SRCS23 – SRCS4
RW +0 RW +0 RW +0 RW +0
RW +0 (per bit field)
Legend: R = Read only; RW = Read/Write; -n = value after reset
7
6
5
4
SRCS3 SRCS2 SRCS1 SRCS0
RW +0 RW +0 RW +0 RW +0
3
1
Reserved
R, +000
0
IPCG
RW +0
Bit
31-4
Field
SRCSx
3-1 Reserved
0
IPCG
Table 4-13. IPC Generation Registers (IPCGRx) Field Descriptions
Description
Interrupt source indication.
Reads return current value of internal register bit.
Writes:
• 0 = No effect
• 1 = Sets both SRCSx and the corresponding SRCCx.
Reserved
Inter-DSP interrupt generation.
Reads return 0.
Writes:
• 0 = No effect
• 1 = Creates an Inter-DSP interrupt.
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