TMS320C6657_15 Datasheet, PDF (153/245 Pages) Texas Instruments – TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor

www.ti.com
TMS320C6655, TMS320C6657
SPRS814B – MARCH 2012 – REVISED APRIL 2015
8.6.4 DDR3 PLL Input Clock Electrical Data/Timing
Table 8-29. DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements
(see Figure 8-24 and Figure 8-20)
NO
MIN
MAX UNIT
DDRCLK[P:N]
1 tc(DDRCLKN)
Cycle time _ DDRCLKN cycle time
3.2
25
ns
1 tc(DDRCLKP)
Cycle time _ DDRCLKP cycle time
3.2
25
ns
3 tw(DDRCLKN)
Pulse width _ DDRCLKN high
0.45*tc(DDRCLKN) 0.55*tc(DDRCLKN)
ns
2 tw(DDRCLKN)
Pulse width _ DDRCLKN low
0.45*tc(DDRCLKN) 0.55*tc(DDRCLKN)
ns
2 tw(DDRCLKP)
Pulse width _ DDRCLKP high
0.45*tc(DDRCLKP) 0.55*tc(DDRCLKP)
ns
3 tw(DDRCLKP)
Pulse width _ DDRCLKP low
0.45*tc(DDRCLKP) 0.55*tc(DDRCLKP)
ns
4 tr(DDRCLK_250mv) Transition time _ DDRCLK differential rise time (250 mV)
50
350
ps
4 tf(DDRCLK_250mv) Transition time _ DDRCLK differential fall time (250 mV)
50
350
ps
5 tj(DDRCLKN)
Jitter, peak_to_peak _ periodic DDRCLKN
0.025*tc(DDRCLKN)
ps
5 tj(DDRCLKP)
Jitter, peak_to_peak _ periodic DDRCLKP
0.025*tc(DDRCLKP)
ps
DDRCLKN
DDRCLKP
1
2
3
4
5
Figure 8-24. DDR3 PLL DDRCLK Timing
Copyright © 2012–2015, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 153
Submit Documentation Feedback