TMS320C6657_15 Datasheet, PDF (82/245 Pages) Texas Instruments – TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor

TMS320C6655, TMS320C6657
SPRS814B – MARCH 2012 – REVISED APRIL 2015
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4.3.11 NMI Event Generation to CorePac (NMIGRx) Register
NMIGRx registers are used for generating NMI events to the corresponding CorePac. The C6657 has two
NMIGRx registers (NMIGR0 and NMIGR1) while the C6655 has only NMIGR0. The NMIGR0 register
generates an NMI event to CorePac0, and the NMIGR1 register generates an NMI event to CorePac1.
Writing a 1 to the NMIG field generates an NMI pulse. Writing a 0 has no effect and reads return 0 and
have no other effect. The NMI Event Generation to CorePac Register is shown in Figure 4-10 and
described in Table 4-12.
Figure 4-10. NMI Generation Register (NMIGRx)
31
Reserved
R, +0000 0000 0000 0000 0000 0000 0000 000
Legend: RW = Read/Write; -n = value after reset
1
0
NMIG
RW,+0
Bit
31-1
0
Field
Reserved
NMIG
Table 4-12. NMI Generation Register (NMIGRx) Field Descriptions
Description
Reserved
NMI pulse generation.
Reads return 0
Writes:
• 0 = No effect
• 1 = Sends an NMI pulse to the corresponding CorePac — CorePac0 for NMIGR0, etc.
82
Device Configuration
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