TMS320C6657_15 Datasheet, PDF (165/245 Pages) Texas Instruments – TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor

www.ti.com
TMS320C6655, TMS320C6657
SPRS814B – MARCH 2012 – REVISED APRIL 2015
Table 8-34. CIC0 Event Inputs (Secondary Interrupts for C66x CorePacs) (continued)
INPUT EVENT# ON CIC SYSTEM INTERRUPT
47
Reserved
48
PCIEXpress_ERR_INT
49
PCIEXpress_PM_INT
50
PCIEXpress_Legacy_INTA
51
PCIEXpress_Legacy_INTB
52
PCIEXpress_Legacy_CIC
53
PCIEXpress_Legacy_INTD
54
SPIINT0
55
SPIINT1
56
SPIXEVT
57
SPIREVT
58
I2CINT
59
I2CREVT
60
I2CXEVT
61
Reserved
62
Reserved
63
TETBHFULLINT
64
TETBFULLINT
65
TETBACQINT
66
TETBOVFLINT
67
TETBUNFLINT
68
SEMINT2
69
SEMINT3
70
SEMERR2
71
SEMERR3
72
Reserved
73
Tracer_core_0_INTD
74
Tracer_core_1_INTD
75
Reserved
76
Reserved
77
Tracer_DDR_INTD
78
Tracer_MSMC_0_INTD
79
Tracer_MSMC_1_INTD
80
Tracer_MSMC_2_INTD
81
Tracer_MSMC_3_INTD
81
Tracer_CFG_INTD
82
Tracer_QM_CFG_INTD
84
Tracer_QM_DMA_INTD
85
Tracer_SM_INTD
86
PSC_ALLINT
87
MSMC_scrub_cerror
88
BOOTCFG_INTD
89
po_vcon_smpserr_intr
90
MPU0_INTD
(MPU0_ADDR_ERR_INT and
MPU0_PROT_ERR_INT combined)
91
Reserved
DESCRIPTION
Protocol error interrupt
Power management interrupt
Legacy interrupt mode
Legacy interrupt mode
Legacy interrupt mode
Legacy interrupt mode
SPI interrupt0
SPI interrupt1
Transmit event
Receive event
I²C interrupt
I²C receive event
I²C transmit event
TETB is half full
TETB is full
Acquisition has been completed
Overflow condition occur
Underflow condition occur
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Tracer sliding time window interrupt for individual core
Tracer sliding time window interrupt for individual core (C6657 only)
Tracer sliding time window interrupt for DDR3 EMIF1
Tracer sliding time window interrupt for MSMC SRAM bank0
Tracer sliding time window interrupt for MSMC SRAM bank1
Tracer sliding time window interrupt for MSMC SRAM bank2
Tracer sliding time window interrupt for MSMC SRAM bank3
Tracer sliding time window interrupt for CFG0 TeraNet
Tracer sliding time window interrupt for QM_SS CFG
Tracer sliding time window interrupt for QM_SS slave
Tracer sliding time window interrupt for semaphore
Power/sleep controller interrupt
Correctable (1-bit) soft error detected during scrub cycle
Chip-level MMR error register
SmartReflex VolCon error status
MPU0 addressing violation interrupt and protection violation interrupt.
Copyright © 2012–2015, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications 165
Submit Documentation Feedback