TMS320C6657_15 Datasheet, PDF (81/245 Pages) Texas Instruments – TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor

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TMS320C6655, TMS320C6657
SPRS814B – MARCH 2012 – REVISED APRIL 2015
4.3.10 Power State Control (PWRSTATECTL) Register
The PWRSTATECTL register is controlled by the software to indicate the power-saving mode. ROM code
reads this register to differentiate between the various power saving modes. This register is cleared only
by POR and will survive all other device resets. See the Hardware Design Guide for KeyStone Devices
(SPRABI2) for more information. The Power State Control Register is shown in Figure 4-9 and described
in Table 4-11.
Figure 4-9. Power State Control Register (PWRSTATECTL)
31
GENERAL_PURPOSE
RW, +0000 0000 0000 0000 0000 0000 0000 0
Legend: RW = Read/Write; -n = value after reset
3
2
1
HIBERNATION
_MODE
HIBERNATION
RW,+0
RW,+0
0
STANDBY
RW,+0
Table 4-11. Power State Control Register (PWRSTATECTL) Field Descriptions
Bit
31-3
Field
GENERAL_PURPOSE
2
HIBERNATION_MODE
1
HIBERNATION
0
STANDBY
Description
Used to provide a start address for execution out of the hibernation modes. See the Bootloader for the
C66x DSP User's Guide (SPRUGY8).
Indicates whether the device is in hibernation mode 1 or mode 2.
• 0 = Hibernation mode 1
• 1 = Hibernation mode 2
Indicates whether the device is in hibernation mode or not.
• 0 = Not in hibernation mode
• 1 = Hibernation mode
Indicates whether the device is in standby mode or not.
• 0 = Not in standby mode
• 1 = Standby mode
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Device Configuration
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