TMS320C6657_15 Datasheet, PDF (184/245 Pages) Texas Instruments – TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor

TMS320C6655, TMS320C6657
SPRS814B – MARCH 2012 – REVISED APRIL 2015
www.ti.com
Table 8-45 shows the privilege ID of each CORE and every mastering peripheral. Table 8-45 also shows
the privilege level (supervisor vs. user), and access type (instruction read vs. data/DMA read or write) of
each master on the device. In some cases, a particular setting depends on software being executed at the
time of the access or the configuration of the master peripheral.
Table 8-45. Privilege ID Settings
PRIVILEGE ID MASTER
0
CorePac0
1
CorePac1 (C6657 only)
2
Reserved
3
Reserved
4
Reserved
5
Reserved
6
uPP
7
EMAC
8
QM_PKTDMA
9
SRIO_Packet DMA/SRIO_M
10
QM_second
11
PCIe
12
DAP
13
HyperLink
14
HyperLink
15
HyperLink
PRIVILEGE LEVEL
SW dependant, driven by MSMC
SW dependant, driven by MSMC
User
User
User
User/Driven by SRIO block, user mode and supervisor mode is
determined on a per-transaction basis. Only the transaction with source ID
matching the value in the SupervisorID Register is granted supervisor
mode.
User
Supervisor
Driven by Debug_SS
Supervisor
Supervisor
Supervisor
ACCESS
TYPE
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
184 Peripheral Information and Electrical Specifications
Copyright © 2012–2015, Texas Instruments Incorporated
Submit Documentation Feedback