TMS320C6657_15 Datasheet, PDF (106/245 Pages) Texas Instruments – TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor

TMS320C6655, TMS320C6657
SPRS814B – MARCH 2012 – REVISED APRIL 2015
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6.1 Memory Architecture
Each C66x CorePac of the device contains a 1024KB level-2 memory (L2), a 32KB level-1 program
memory (L1P), and a 32KB level-1 data memory (L1D). The C665x devices also contain a 1024KB
multicore shared memory (MSM). All memory on the C665x has a unique location in the memory map
(see Table 3-2).
After device reset, L1P and L1D cache are configured as all cache, by default. The L1P and L1D cache
can be reconfigured via software through the L1PMODE field of the L1P Configuration Register (L1PCFG)
and the L1DMODE field of the L1D Configuration Register (L1DCFG) of the C66x CorePac. L1D is a two-
way set-associative cache, while L1P is a direct-mapped cache.
The on-chip bootloader changes the reset configuration for L1P and L1D. For more information, see the
Bootloader for the C66x DSP User's Guide (SPRUGY5).
For more information on the operation L1 and L2 caches, see the C66x DSP Cache User's Guide
(SPRUGY8).
6.1.1 L1P Memory
The L1P memory configuration for the C665x device is as follows:
• 32K bytes with no wait states
Figure 6-2 shows the available SRAM/cache configurations for L1P.
L1P mode bits
000
001
010
011
100
L1P memory
Block base
address
00E0 0000h
All
SRAM
7/8
SRAM
3/4
SRAM
1/2
SRAM
direct
mapped
cache
dm
cache
direct
mapped
cache
direct
mapped
cache
16K bytes
8K bytes
4K bytes
4K bytes
Figure 6-2. L1P Memory Configurations
00E0 4000h
00E0 6000h
00E0 7000h
00E0 8000h
106 C66x CorePac
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