TMS320C6657_15 Datasheet, PDF (146/245 Pages) Texas Instruments – TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor

TMS320C6655, TMS320C6657
SPRS814B – MARCH 2012 – REVISED APRIL 2015
www.ti.com
8.5.2.8 Reset Configuration Register (RSTCFG)
This register is used to configure the type of reset initiated by RESET, watchdog timer and the PLL
controller’s RSTCTRL Register; i.e., a hard reset or a soft reset. By default, these resets will be hard
resets. The Reset Configuration Register (RSTCFG) is shown in Figure 8-15 and described in Table 8-22.
Figure 8-15. Reset Configuration Register (RSTCFG)
31
14
13
12
11
4
3
0
Reserved
PLLCTLRST
TYPE
RESETTYPE
Reserved
WDTYPE[N ⁽¹⁾]
R-0
R/W-0 ⁽²⁾
R/W-0²
R-0
R/W-0²
Legend: R = Read only; R/W = Read/Write; -n = value after reset
(1) Where N = 1, 2, 3,....N (Not all these output may be used on a specific device. For more information, see the device-specific data
manual)
(2) Writes are conditional based on valid key. For details, see Section 8.5.2.7.
Table 8-22. Reset Configuration Register (RSTCFG) Field Descriptions
Bit
31-14
13
Field
Reserved
PLLCTLRSTTYPE
12
RESETTYPE
11-4
3
Reserved
WDTYPE3
2
WDTYPE2
1
WDTYPE1
0
WDTYPE0
Description
Reserved.
PLL controller initiates a software-driven reset of type:
• 0 = Hard reset (default)
• 1 = Soft reset
RESET initiates a reset of type:
• 0 = Hard Reset (default)
• 1 = Soft Reset
Reserved.
Watchdog timer [N] initiates a reset of type:
• 0 = Hard Reset (default)
• 1 = Soft Reset
Watchdog timer [N] initiates a reset of type:
• 0 = Hard Reset (default)
• 1 = Soft Reset
Watchdog timer [N] initiates a reset of type:
• 0 = Hard Reset (default)
• 1 = Soft Reset
Watchdog timer [N] initiates a reset of type:
• 0 = Hard Reset (default)
• 1 = Soft Reset
146 Peripheral Information and Electrical Specifications
Copyright © 2012–2015, Texas Instruments Incorporated
Submit Documentation Feedback