TMS320C6657_15 Datasheet, PDF (26/245 Pages) Texas Instruments – TMS320C6655 and TMS320C6657 Fixed and Floating-Point Digital Signal Processor

TMS320C6655, TMS320C6657
SPRS814B – MARCH 2012 – REVISED APRIL 2015
www.ti.com
3.5.2.7 SPI Boot Device Configuration
In SPI boot mode, the SPI device configuration uses ten bits of device configuration instead of seven as
used in other boot modes.
Figure 3-13. SPI Device Configuration Bit Fields
12
11
Mode
10
4, 5 Pin
9
Addr Width
8
7
Chip Select
6
5
4
3
Parameter Table Index
Bit
12-11
Field
Mode
10
4, 5 Pin
9
Addr Width
8-7
Chip Select
6-3
Parameter Table
Index
Table 3-15. SPI Device Configuration Field Descriptions
Description
Clk Pol / Phase
• 0 = Data is output on the rising edge of SPICLK. Input data is latched on the falling edge.
• 1 = Data is output one half-cycle before the first rising edge of SPICLK and on subsequent falling
edges. Input data is latched on the rising edge of SPICLK.
• 2 = Data is output on the falling edge of SPICLK. Input data is latched on the rising edge.
• 3 = Data is output one half-cycle before the first falling edge of SPICLK and on subsequent rising
edges. Input data is latched on the falling edge of SPICLK.
SPI operation mode configuration
• 0 = 4-pin mode used
• 1 = 5-pin mode used
SPI address width configuration
• 0 = 16-bit address values are used
• 1 = 24-bit address values are used
The chip select field value
Specifies which parameter table is loaded
26
Device Overview
Submit Documentation Feedback
Copyright © 2012–2015, Texas Instruments Incorporated