TL16C550D_09 Datasheet, PDF (8/54 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

TL16C550D, TL16C550DI
SLLS597E – APRIL 2004 – REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
TERMINAL
NAME
NO.
A0
28
A1
27
A2
26
ADS
24
BAUDOUT
12
CS0
9
CS1
10
CS2
11
CTS
38
D0
43
D1
44
D2
45
D3
46
D4
47
D5
2
D6
3
D7
4
DCD
40
DDIS
22
DSR
39
DTR
33
INTRPT
MR
NC
OUT1
OUT2
RCLK
RD1
RD2
30
35
1,6,13,
21, 25, 36,
37, 48
34
31
5
19
20
TERMINAL FUNCTIONS (FOR PT/PFB PACKAGES)
I/O
DESCRIPTION
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Register select. A0−A2 are used during read and write operations to select the ACE register
to read from or write to. See Table 1 for register addresses, and see the ADS description.
Address strobe. When ADS is active (low), A0, A1, and A2 and CS0, CS1, and CS2 drive the
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internal select logic directly; when ADS is high, the register select and chip select signals are
held at the logic levels they were in when the low-to-high transition of ADS occurred.
Baud out. BAUDOUT is a 16× clock signal for the transmitter section of the ACE. The clock
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rate is established by the reference oscillator frequency divided by a divisor specified by the
baud generator divisor latches. BAUDOUT may also be used for the receiver section by tying
this output to RCLK.
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Chip select. When CS0 and CS1 are high and CS2 is low, these three inputs select the ACE.
When any of these inputs are inactive, the ACE remains inactive (see the ADS description).
Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4
(CTS) of the modem status register. Bit 0 (ΔCTS) of the modem status register indicates that
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CTS has changed states since the last read from the modem status register. If the modem
status interrupt is enabled when CTS changes levels and the auto-CTS mode is not enabled,
an interrupt is generated. CTS is also used in the auto-CTS mode to control the transmitter.
I/O
Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control,
and status information between the ACE and the CPU.
Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading
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bit 7 (DCD) of the modem status register. Bit 3 (ΔDCD) of the modem status register
indicates that DCD has changed states since the last read from the modem status register. If
the modem status interrupt is enabled when DCD changes levels, an interrupt is generated.
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Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDIS
can disable an external transceiver.
Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5
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(DSR) of the modem status register. Bit 1 (ΔDSR) of the modem status register indicates
DSR has changed levels since the last read from the modem status register. If the modem
status interrupt is enabled when DSR changes levels, an interrupt is generated.
Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is
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ready to establish communication. DTR is placed in the active level by setting the DTR bit of
the modem control register. DTR is placed in the inactive level either as a result of a master
reset, during loop mode operation, or clearing the DTR bit.
Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be
serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received
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data that is available or timed out (FIFO mode only), an empty transmitter holding register, or
an enabled modem status interrupt. INTRPT is reset (deactivated) either when the interrupt
is serviced or as a result of a master reset.
Master reset. When active (high), MR clears most ACE registers and sets the levels of
various output signals (see Table 2).
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No connection
Outputs 1 and 2. These are user-designated output terminals that are set to the active (low)
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level by setting respective modem control register (MCR) bits (OUT1 and OUT2). OUT1 and
OUT2 are set to inactive the (high) level as a result of master reset, during loop mode
operations, or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the MCR.
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Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE.
Read inputs. When either RD1 or RD2 is active (low or high, respectively) while the ACE is
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selected, the CPU is allowed to read status information or data from a selected ACE register.
Only one of these inputs is required for the transfer of data during a read operation; the other
input must be tied to its inactive level (i.e., RD2 tied low or RD1 tied high).
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