TL16C550D_09 Datasheet, PDF (33/54 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

TL16C550D, TL16C550DI
www.ti.com .................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
0DLAB =
0
0DLAB = 0
1DLAB = 0
2
2
3
4
5
6
7
0DLAB = 1 1DLAB = 1
BIT
NO.
Receiver
Buffer
Register
(Read
Only)
Transmitter
Holding
Register
(Write Only)
Interrupt
Enable
Register
Interrupt
Indent.
Register
(Read Only)
FIFO
Control
Register
(Write Only)
Line
Control
Register
Modem
Control
Register
Line Status
Register
Modem
Status
Register
Scratch
Divisor
Register Latch (LSB)
Latch
(MSB)
RBR
THR
IER
IIR
FCR
LCR
MCR
LSR
MSR
SCR
DLL
DLM
Enable
0
Data Bit
0 ⁽¹⁾
Data Bit 0
Received
Data
Available
Interrupt
0 if Interrupt
Pending
FIFO Enable
Word
Length
Select Bit
0 (WLS0)
Data Terminal Data Ready
Ready
(DR)
Delta Clear
to Send
(ΔCTS)
Bit 0
(ERBI)
Bit 0
Bit 8
Enable
1
Data Bit 1
Data Bit 1
Transmitter
Holding
Register
Empty
Interrupt
Interrupt ID
Bit 1
Receiver
FIFO Reset
Word
Length
Select Bit
1 (WLS1)
Request to
Send (RTS)
Overrun
Error (OE)
Delta Data
Set Ready
(ΔDSR)
(ETBEI)
Bit 1
Bit 1
Bit 9
Enable
2
Data Bit 2
Data Bit 2
Receiver
Line Status
Interrupt
Interrupt ID
Bit 2
Transmitter
FIFO Reset
Number of
Stop Bits
(STB)
(ELSI)
OUT1
Parity Error
(PE)
Trailing
Edge Ring
Indicator
(TERI)
Bit 2
Bit 2
Bit 10
Enable
3
Data Bit 3 Data Bit 3
Modem
Status
Interrupt
Interrupt ID DMA Mode
Bit 3⁽²⁾
Select
Parity
Enable
(PEN)
(EDSSI)
OUT2
Framing
Error (FE)
Delta Data
Carrier
Detect
(ΔDCD)
Bit 3
Bit 3
Bit 11
4
Data Bit 4 Data Bit 4
0
Even
0
Reserved
Parity
Select
Loop
Break
Interrupt
Clear to
Send (CTS)
Bit 4
Bit 4
Bit 12
(EPS)
5
Data Bit 5 Data Bit 5
0
0
Reserved
Stick
Parity
Autoflow
Control Enable
(AFE)
Transmitter
Holding
Register
(THRE)
Data Set
Ready
(DSR)
Bit 5
Bit 5
Bit 13
6
Data Bit 6 Data Bit 6
0
FIFOs
Enabled ⁽²⁾
Receiver
Trigger
(LSB)
Break
Control
Transmitter
Ring
0
Empty
Indicator
Bit 6
Bit 6
Bit 14
(TEMT)
(RI)
7
Data Bit 7 Data Bit 7
0
Receiver
Trigger
(MSB)
Divisor
Latch
Access Bit
(DLAB)
0
Error in
RCVR
FIFO⁽²⁾
Data Carrier
Detect
(DCD)
Bit 7
Bit 7
Bit 15
(1) Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
(2) These bits are always 0 in the TL16C450 mode.
FIFO Control Register (FCR)
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
and clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signaling.
• Bit 0: This bit, when set, enables the transmitter and receiver FIFOs. Bit 0 must be set when other FCR bits
are written to or they are not programmed. Changing this bit clears the FIFOs.
• Bit 1: This bit, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.
• Bit 2: This bit, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not
cleared. The 1 that is written to this bit position is self-clearing.
• Bit 3: When FCR0 is set, setting FCR3 causes RXRDY and TXRDY to change from level 0 to level 1.
• Bits 4 and 5: These two bits are reserved for future use.
• Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt (see Table 4).
Copyright © 2004–2008, Texas Instruments Incorporated
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