TL16C550D_09 Datasheet, PDF (32/54 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

TL16C550D, TL16C550DI
SLLS597E – APRIL 2004 – REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
PRINCIPLES OF OPERATION
DLAB ⁽¹⁾
A2
0
L
0
L
X
L
X
L
X
L
X
H
X
H
X
H
X
H
1
L
1
L
Table 1. Register Selection
A1
A0
REGISTER
L
L
Receiver buffer (read), transmitter holding register (write)
L
H
Interrupt enable register
H
L
Interrupt identification register (read only)
H
L
FIFO control register (write)
H
H
Line control register
L
L
Modem control register
L
H
Line status register
H
L
Modem status register
H
H
Scratch register
L
L
Divisor latch (LSB)
L
H
Divisor latch (MSB)
(1) The divisor latch access bit (DLAB) is the most significant bit (MSB) of the line control register. The
DLAB signal is controlled by writing to this bit location (see Table 4).
REGISTER/SIGNAL
Interrupt enable register
Interrupt identification register
FIFO control register
Line control register
Modem control register
Line status register
Modem status register
SOUT
INTRPT (receiver error flag)
INTRPT (received data available)
INTRPT (transmitter holding register empty)
INTRPT (modem status changes)
OUT2
RTS
DTR
OUT1
Scratch register
Divisor latch (LSB and MSB) registers
Receiver buffer register
Transmitter holding register
RCVR FIFO
XMIT FIFO
Table 2. ACE Reset Functions
RESET CONTROL
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Read LSR/MR
Read RBR/MR
Read IR/write THR/MR
Read MSR/MR
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
Master reset
MR/FCR1 – FCR0/ΔFCR0
MR/FCR2 – FCR0/ΔFCR0
RESET STATE
All bits cleared (0−3 forced and 4−7 permanent)
Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and bits
4−5 are permanently cleared
All bits cleared
All bits cleared
All bits cleared (6−7 permanent)
Bits 5 and 6 are set; all other bits are cleared
Bits 0−3 are cleared; bits 4−7 are input signals
High
Low
Low
Low
Low
High
High
High
High
No effect
No effect
No effect
No effect
All bits cleared
All bits cleared
Accessible Registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions of
these registers follow Table 3.
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