TL16C550D_09 Datasheet, PDF (17/54 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

TL16C550D, TL16C550DI
www.ti.com .................................................................................................................................................. SLLS597E – APRIL 2004 – REVISED DECEMBER 2008
SYSTEM SWITCHING CHARACTERISTICS⁽¹⁾
over recommended ranges of supply voltage and operating free-air temperature
PARAMETER
t_dis(R) Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓
ALT. SYMBOL
TEST CONDITIONS
t_RDD
C_L = 75 pF, Figure 7
(1) Charge and discharge are determined by V_OL, V_OH, and external loading.
MIN MAX UNIT
20
ns
BAUD GENERATOR SWITCHING CHARACTERISTICS
over recommended ranges of supply voltage and operating free-air temperature, C_L = 75 pF (For PT and PFB packages only)
PARAMETER
ALT. SYMBOL
TEST CONDITIONS
MIN MAX UNIT
t_w3 Pulse duration, BADOUT low
t_w4 Pulse duration, BADOUT high
t_d1 Delay time, XIN↑ to BADOUT↑
t_d2 Delay time, XIN↑↓ to BADOUT↓
t_LW
t_HW
f = 24 MHz, CLK ÷ 2, V_CC = 5 V,
See Figure 5
35
ns
t_BLD
See Figure 5
45 ns
t_BHD
See Figure 5
45 ns
RECEIVER SWITCHING CHARACTERISTICS⁽¹⁾
over recommended ranges of supply voltage and operating free-air temperature
PARAMETER
t_d12 Delay time, RCLK to sample
t_d13
Delay time, stop to set INTRPT or read
RBR to lSI interrupt or stop to RXRDY↓
t_d14 Delay time, read RBR/LSR to reset INTRPT
ALT. SYMBOL
t_SCD
t_SINT
t_RINT
TEST CONDITIONS
See Figure 8
See Figure 5, Figure 9,
Figure 10, Figure 11,
Figure 12
C_L = 75 pF,
See Figure 5, Figure 9,
Figure 10, Figure 11,
Figure 12
MIN MAX UNIT
10 ns
RCL
1K
cycle
70 ns
(1) In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receive FIFO and the status registers (interrupt identification
register or line status register).
TRANSMITTER SWITCHING CHARACTERISTICS⁽¹⁾
over recommended ranges of supply voltage and operating free-air temperature
PARAMETER
ALT. SYMBOL
TEST CONDITIONS
t_d15 Delay time, initial write to transmit start
t_IRS
See Figure 13
t_d16 Delay time, start to INTRPT
t_d17 Delay time, WR1 (WR THR) to reset INTRPT
t_d18 Delay time, initial write to INTRPT (THRE⁽¹⁾)
t_d19 Delay time, read IIR⁽²⁾ to reset INTRPT (THRE⁽¹⁾)
t_d20 Delay time, write to TXRDY inactive
t_d21 Delay time, start to TXRDY active
(1) THRE = transmitter holding register empty
(2) IIR = Interrupt identification register
t_STI
See Figure 13
t_HR
C_L = 75 pF,
See Figure 13
t_SI
See Figure 13
t_IR
C_L = 75 pF,
See Figure 13
t_WXI
C_L = 75 pF,
See Figure 14 and Figure 15
t_SXA
C_L = 75 pF,
See Figure 14 and Figure 15
MIN MAX UNIT
8
24
baudout
cycles
8
10
baudout
cycles
50 ns
16
34
baudout
cycles
35 ns
35 ns
9
baudout
cycles
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