TL16C550D_09 Datasheet, PDF (12/54 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

TL16C550D, TL16C550DI
SLLS597E – APRIL 2004 – REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
TERMINAL
NAME
NO.
A0
D5
A1
E5
A2
E4
CS2
D1
CTS
C4
D0
A4
D1
B4
D2
A3
D3
B3
D4
A2
D5
A1
D6
C3
D7
B1
INTRPT
D4
MR
B5
RD1
D3
RTS
C5
SIN
C1
SOUT
C2
V_CC
A5
V_SS
E3
WR1
D2
XIN
E1
XOUT
E2
TERMINAL FUNCTIONS (FOR ZQS PACKAGE)
I/O
DESCRIPTION
I
Register select. A0−A2 are used during read and write operations to select the ACE register
to read from or write to. See Table 1 for register addresses, and see the ADS description.
I
Chip select. When CS2 is low, the ACE is selected. When CS2 is high, the ACE remains
inactive.
Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4
(CTS) of the modem status register. Bit 0 (ΔCTS) of the modem status register indicates that
I
CTS has changed states since the last read from the modem status register. If the modem
status interrupt is enabled when CTS changes levels and the auto-CTS mode is not enabled,
an interrupt is generated. CTS is also used in the auto-CTS mode to control the transmitter.
I/O
Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control,
and status information between the ACE and the CPU.
Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be
serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received
O
data that is available or timed out (FIFO mode only), an empty transmitter holding register, or
an enabled modem status interrupt. INTRPT is reset (deactivated) either when the interrupt
is serviced or as a result of a master reset.
Master reset. When active (high), MR clears most ACE registers and sets the levels of
various output signals (see Table 2).
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Read input. When RD1 is active (low) while the ACE is selected, the CPU is allowed to read
status information or data from a selected ACE register.
Request to send. When active, RTS informs the modem or data set that the ACE is ready to
receive data. RTS is set to the active level by setting the RTS modem control register bit and
O
is set to the inactive (high) level either as a result of a master reset or during loop mode
operations or by clearing bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS is set to the
inactive level by the receiver threshold control logic.
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Serial data input. SIN is serial data input from a connected communications device.
O
Serial data output. SOUT is composite serial data output to a connected communication
device. SOUT is set to the marking (high) level as a result of master reset.
2.25-V to 5.5-V power supply voltage
Supply common, ground
I
Write input. When WR1 is active (low) and while the ACE is selected, the CPU is allowed to
write control words or data into a selected ACE register.
I/O
External clock. XIN and XOUT connect the ACE to the main timing reference (clock or
crystal).
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