TL16C550D_09 Datasheet, PDF (36/54 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

TL16C550D, TL16C550DI
SLLS597E – APRIL 2004 – REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
INTERRUPT IDENTIFICATION
REGISTER
BIT 3 BIT 2 BIT 1 BIT 0
0
0
1
0
0
0
0
0
Table 5. Interrupt Control Functions (continued)
PRIORITY
LEVEL
INTERRUPT TYPE
INTERRUPT SOURCE
INTERRUPT RESET
METHOD
Read the interrupt
3
Transmitter holding
register empty
Transmitter holding register
empty
identification register (if source
of interrupt) or writing into the
transmitter holding register
4
Modem status
Clear to send, data set ready,
ring indicator, or data carrier
detect
Read the modem status
register
Line Control Register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and described in the following bulleted list.
• Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character. These
bits are encoded as shown in Table 6.
Table 6. Serial Character
Word Length
BIT 1
0
0
1
1
BIT 0
0
1
0
1
WORD LENGTH
5 bits
6 bits
7 bits
8 bits
• Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When bit
2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated is
dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit regardless
of the number of stop bits selected. The number of stop bits generated in relation to word length and bit 2 are
shown in Table 7.
Table 7. Number of Stop Bits Generated
BIT 2
0
1
1
1
1
WORD LENGTH
SELECTED
BY BITS 1 AND 2
Any word length
5 bits
6 bits
7 bits
8 bits
NUMBER OF STOP
BITS GENERATED
1
1＝
2
2
2
• Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is
cleared, no parity is generated or checked.
• Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity (an
even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is cleared,
odd parity (an odd number of logic 1s) is selected.
• Bit 5: This bit is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as
cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. If bit 5
is cleared, stick parity is disabled.
• Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT is
forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled and has no effect
on the transmitter logic; it only effects SOUT.
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