TL16C550D_09 Datasheet, PDF (40/54 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

TL16C550D, TL16C550DI
SLLS597E – APRIL 2004 – REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
Table 10. Baud Rates Using a 3.072-MHz
Crystal (continued)
DESIRED
BAUD RATE
1800
2000
2400
3600
4800
7200
9600
19200
38400
DIVISOR USED
TO GENERATE
16× CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
107
0.312
96
80
53
0.628
40
27
1.23
20
10
5
TYPICAL CRYSTAL OSCILLATOR NETWORK
CRYSTAL
3.072 MHz
1.8432 MHz
16 MHz
R_p
1 MΩ
1 MΩ
1 MΩ
RX2
1.5 kΩ
1.5 kΩ
0Ω
C1
C2
10 – 30 pF 40 – 60 pF
10 – 30 pF 40 – 60 pF
33 pF
33 pF
Figure 27. Typical Clock Circuits
Receiver Buffer Register (RBR)
The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte
FIFO. Timing is supplied by the 16＝ receiver clock (RCLK). Receiver section control is a function of the ACE
line control register.
The ACE RSR receives serial data from SIN. The RSR then concatenates the data and moves it into the RBR
FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available interrupt is
enabled (IER0 = 1), an interrupt is generated. This interrupt is cleared when the data is read out of the RBR. In
the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.
40
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