TL16C550D_09 Datasheet, PDF (16/54 Pages) Texas Instruments – ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL

TL16C550D, TL16C550DI
SLLS597E – APRIL 2004 – REVISED DECEMBER 2008 .................................................................................................................................................. www.ti.com
SYSTEM TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature
t_cR Cycle time, read (t_w7 + t_d8 + t_d9)
t_cW Cycle time, write (t_w6 + t_d5 + t_d6)
t_w1 Pulse duration, clock high
t_w2 Pulse duration, clock low
t_w5 Pulse duration, ADS low
t_w6 Pulse duration, WR
t_w7 Pulse duration, RD
t_w8 Pulse duration, MR
t_su1 Setup time, address valid before ADS↑
t_su2 Setup time, CS valid before ADS↑
t_su3 Setup time, data valid before WR1↑ or WR2↓
t_su4 Setup time, CTS↑ before midpoint of stop bit
t_h1 Hold time, address low after ADS↑
t_h2 Hold time, CS valid after ADS↑
t_h3 Hold time, CS valid after WR1↑ or WR2↓
t_h4 Hold time, address valid after WR1↑ or WR2↓
t_h5 Hold time, data valid after WR1↑ or WR2↓
t_h6 Hold time, CS valid after RD1↑ or RD2↓
t_h7 Hold time, address valid after RD1↑ or RD2↓
t_d4 Delay time, CS valid before WR1↓ or WR2↑⁽¹⁾
t_d5 Delay time, address valid before WR1↓ or WR2↑⁽¹⁾
t_d6 Delay time, write cycle, WR1↑ or WR2↓ to ADS↓
t_d7 Delay time, CS valid to RD1↓ or RD2↑⁽¹⁾
t_d8 Delay time, address valid to RD1↓ or RD2↑⁽¹⁾
t_d9 Delay time, read cycle, RD1↑ or RD2↓ to ADS↓
t_d10 Delay time, RD1↓ or RD2↑ to data valid
t_d11 Delay time, RD1↑ or RD2↓ to floating data
ALT. SYMBOL
RC
WC
t_XH
t_XL
tADS
t_WR
t_RD
t_MR
t_AS
t_CS
tDS
t_AH
t_CH
t_WCS
t_WA
t_DH
t_RCS
t_RA
t_CSW
t_AW
t_WC
tCSR
t_AR
t_RC
t_RVD
t_HZ
TEST CONDITIONS
f = 16 MHz Max, V_CC = 2.5 V,
See Figure 5
f = 20 MHz Max, V_CC = 3.3 V,
See Figure 5
f = 24 MHz Max, V_CC = 5 V,
See Figure 5
f = 48 MHz Max, V_CC = 3.3 V,
See Figure 5
(ZQS package only)
f = 16 MHz Max, V_CC = 2.5 V,
See Figure 5
f = 20 MHz Max, V_CC = 3.3 V,
See Figure 5
f = 24 MHz Max, V_CC = 5 V,
See Figure 5
f = 48 MHz Max, V_CC = 3.3 V,
See Figure 5
(ZQS package only)
See Figure 6 and Figure 7
See Figure 6
See Figure 7
See Figure 6 and Figure 7
See Figure 6
See Figure 17
See Figure 6 and Figure 7
See Figure 6
See Figure 6
See Figure 7
See Figure 6
See Figure 6
See Figure 6
See Figure 7
See Figure 7
C_L = 75 pF, Figure 7
C_L = 75 pF, See Figure 7
(1) Only applies when ADS is low.
MIN MAX UNIT
87
ns
87
ns
25
20
ns
18
8
25
20
ns
18
8
9
ns
40
ns
40
ns
1
µs
8
ns
15
ns
10
ns
0
ns
10
ns
5
ns
10
ns
20
ns
7
ns
40
ns
7
ns
40
ns
45 ns
20 ns
16
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