TMS320C6A8167 Datasheet, PDF (78/280 Pages) Texas Instruments – TMS320C6A816x Integra DSP+ARM Processors

TMS320C6A8168
TMS320C6A8167
SPRS680 – OCTOBER 2010
www.ti.com
3.2.11 Peripheral Component Interconnect Express (PCIe) Signals
Table 3-14. PCIe Terminal Functions
SIGNAL
NAME
TYPE ⁽¹⁾
NO.
OTHER ⁽²⁾
DESCRIPTION
PCIE_TXP0
PCIE_TXN0
AB31
O
PCIE Transmit Data Lane 0.
AB30
O
VDDR_PCIE _{When the PCIe SERDES are powered down, these pins should be left}
unconnected.
PCIE_RXP0
PCIE_RXN0
Y29
I
PCIE Receive Data Lane 0.
V29
I
VDDR_PCIE _{When the PCIe SERDES are powered down, these pins should be left}
unconnected.
PCIE_TXP1
PCIE_TXN1
Y27
O
PCIE Transmit Data Lane 1.
AB28
O
VDDR_PCIE _{When the PCIe SERDES are powered down, these pins should be left}
unconnected.
PCIE_RXP1
PCIE_RXN1
V31
I
PCIE Receive Data Lane 1.
V30
I
VDDR_PCIE _{When the PCIe SERDES are powered down, these pins should be left}
unconnected.
SERDES_CLKP
SERDES_CLKN
AB34
I
AB33
I
VDD_LJCB
VDD_LJCB
PCIE Serdes Reference Clock Inputs. Shared between PCI Express and
Serial ATA. When neither PCI Express nor Serial ATA are used, these
pins should be left unconnected.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal
(2) Specifies the operating I/O supply voltage for each signal
78
Device Pins
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