TMS320C6A8167 Datasheet, PDF (145/280 Pages) Texas Instruments – TMS320C6A816x Integra DSP+ARM Processors

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from the main PLL output
• H = 10 if M * FREQ is a multiple of 8; otherwise, H = 0
• 800 MHz ≤ PLL_CLKIN * N / P ≤ 1600 MHz
• 10 MHz ≤ PLL_CLKIN / P ≤ 60 MHz
TMS320C6A8168
TMS320C6A8167
SPRS680 – OCTOBER 2010
CLOCK
Main PLL
Clock1
Clock2
Clock3
Clock4
DDR PLL
Clock 2
Clock 3
Video PLL
Clock 1
Clock 2
Clock 3
Audio PLL
Clock 2
Clock 3
Clock 4
Clock 5
Table 7-12. PLL Clock Frequencies
MIN CYCLE
MAX FREQUENCY
985
842
1847
1991
987
1152
532
494
18447
54
2443
405
1485
660
1485
660
1485
660
6290
158
5041
197
10000
100
10000
100
7.3.4.2 PLL Power Supply Filtering
The device PLLs are supplied externally via the VDDA_PLL power-supply pins. External filtering must be
added on the PLL supply pins to ensure that the requirements in Table 7-13 are met.
Table 7-13. Power Supply Requirements
Dynamic noise at VDDA_PLL pins
PARAMETER
MIN
MAX UNIT
50 mV p-p
7.3.4.3 PLL Locking Sequence
All of the flying-adder PLLs (except the DDR PLL) come-up in bypass mode at reset. All of the registers
(P, N, FREQ, and M) need to be programmed appropriately and then wait approximately 8 µs for
PLL_Audio and 5 µs for the other PLLS to be locked. Verification that the PLL is locked can be checked
by accessing the lock status bit in the PLL control register for each PLL (bit = 1 when the PLL is locked).
Once the PLL is locked, then the FA-PLL can be taken out of bypass mode. Control for bypass mode is
through chip-level registers. For more details on the PLL registers and bypass logic, see the PLL chapter
of the TMS320C6A8x Integra DSP+ARM Processors Technical Reference Manual (literature number
SPRUGX9).
7.3.4.4 PLL Registers
The PLL control registers reside in the control module and are listed in Table 4-3.
Copyright © 2010, Texas Instruments Incorporated
Power, Reset, Clocking, and Interrupts 145
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