TMS320C6A8167 Datasheet, PDF (128/280 Pages) Texas Instruments – TMS320C6A816x Integra DSP+ARM Processors

TMS320C6A8168
TMS320C6A8167
SPRS680 – OCTOBER 2010
www.ti.com
6.2 Recommended Operating Conditions⁽¹⁾
CVDD
CVDDC
DVDD
VSS
DDR_VREF
V_IH
V_IL
I_OH
I_OL
V_ID
t_t
PARAMETER
Supply voltage, Variable Core, Adaptive Voltage
Scaling (CVDD)⁽²⁾
Supply voltage, Constant Core (CVDDC,
VDDT_SATA, VDDT_PCIE, VDDA_HDMI,
VDDA_HD_1P0, VDDA_SD_1P0)
Supply voltage, I/O, 3.3 V (DVDD_3P3,
VDD_USB0_3P3, VDD_USB1_3P3)
(except I2C pins)
Supply voltage, I/O, I2C (DVDD_3P3)
Supply voltage, I/O, 1.8 V (DVDD1P8,
DEVOSC_DVDD18, VDD_USB0_1P8,
VDD_USB1_1P8, VDDA_REF_1P8,
VDDA_HD_1P8, VDDA_SD_1P8, DVDD_DDR0,
DVDD_DDR1) ⁽³⁾
Supply voltage, I/O, 1.5 V (VDDA_PLL,
VDDR_SATA, VDDR_PCIE, DVDD_DDR0,
DVDD_DDR1) ⁽³⁾
Supply voltage, I/O, 0.9 V (VDD_USB_0P9)
Supply ground (VSS, VSSA_PLL, VSSA_HD,
VSSA_SD, VSSA_REF_1P8, DEVOSC_VSS)⁽⁴⁾
DDR2/3 reference voltage⁽⁵⁾
High-level input voltage, 3.3 V (except I2C pins)
High-level input voltage, I2C
High-level input voltage, 1.8 V
Low-level input voltage, 3.3 V (except I2C pins)
Low-level input voltage, I2C
Low-level input voltage, 1.8 V
4-mA I/O buffers
High-level output current
6-mA I/O buffers
DDR[0], DDR[1]
buffers @ 50-Ω
impedance setting
4-mA I/O buffers
Low-level output current
6-mA I/O buffers
DDR[0], DDR[1]
buffers @ 50-Ω
impedance setting
Differential input voltage (SERDES_CLKN/P),
[AC coupled]
Transition time, 10%-90%, All Inputs (unless
otherwise specified in the electrical data sections)
MIN
0.8
0.95
3.13
3.13
1.71
1.43
0.85
0
0.48DVDD_DDRx
2
0.7DVDD_3P3
0.65DVDD1P8
0.25
NOM
1
3.3
3.3
1.8
MAX UNIT
1.05 V
1.05 V
3.47 V
3.47 V
1.89 V
1.5
1.58 V
0.9
0.95 V
0
0V
0.5DVDD_DDRx 0.52DVDD_DDRx V
V
0.8
0.3DVDD_3P3 V
0.35DVDD1P8
-4
-6
mA
-8
4
6
mA
8
2.0 V
Lesser of 0.25P or
10 ⁽⁶⁾
ns
(1) Data in this table is based on device operation at 1.0 GHz for the ARM Cortex-A8 and 800 MHz for the C674x DSP.
(2) This device supports, and requires the use of, SmartReflex technology with Adaptive Voltage Scaling based on die temperature and
performance. The SmartReflex codes output from the device correspond to up to 32 linear voltage steps within the specified voltage
range, with the option to use fewer steps if desired, with a minimum of eight steps. TI requires that users design-in a supply that can
handle multiple voltage steps within this range with ± 5% tolerances. Not incorporating a flexible supply may limit the system's ability to
use the power saving capabilities of the SmartReflex technology.
(3) For supply voltage pins, DVDD_DDRx:
• 1.5 V is used for DDR3 SDRAM.
• 1.8 V is used for DDR2 SDRAM.
(4) Oscillator ground (DEVOSC_VSS) must be kept separate from other grounds and connected directly to the crystal load capacitor
ground.
(5) DDR_VREF is expected to equal 0.5DVDD_DDRx of the transmitting device and to track variations in the DVDD_DDRx.
(6) P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve noise immunity on input
signals.
128 Device Operating Conditions
Copyright © 2010, Texas Instruments Incorporated
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