TMS320C6A8167 Datasheet, PDF (1/280 Pages) Texas Instruments – TMS320C6A816x Integra DSP+ARM Processors

www.ti.com
TMS320C6A816x Integra
DSP+ARM Processors
Check for Samples: TMS320C6A8168, TMS320C6A8167
TMS320C6A8168
TMS320C6A8167
SPRS680 – OCTOBER 2010
1 Device Summary
1.1 Features
1234567891011
• High-Performance Integra™ DSP+ARM^®
Processors
– ARM^® Cortex™-A8 RISC MPU
• Up to 1.5 GHz
– C674x VLIW DSP
• Up to 1.5 GHz
• 10000/7500 C674x MIPS/MFLOPS
• Fully Software-Compatible with C67x+™
and C64x+™
• ARM^® Cortex™-A8 Core
– ARMv7 Architecture
• In-Order, Dual-Issue, Superscalar
Microprocessor Core
• NEON™ Multimedia Architecture
– Supports Integer and Floating Point
(VFPv3-IEEE754 compliant)
• Jazelle^® RCT Execution Environment
• ARM^® Cortex™-A8 Memory Architecture
– 32K-Byte Instruction and Data Caches
– 256K-Byte L2 Cache
– 64K-Byte RAM, 48K-Byte Boot ROM
• TMS320C674x Floating-Point VLIW DSP
– 64 General-Purpose Registers (32-Bit)
– Six ALU (32-/40-Bit) Functional Units
• Supports 32-Bit Integer, SP (IEEE Single
Precision/32-Bit) and DP (IEEE Double
Precision/64-Bit) Floating Point
• Supports up to Four SP Adds Per Clock
and Four DP Adds Every Two Clocks
• Supports up to Two Floating-Point (SP or
DP) Approximate Reciprocal or Square
Root Operations Per Cycle
– Two Multiply Functional Units
• Mixed-Precision IEEE Floating-Point
Multiply Supported up to:
– 2 SP x SP → SP Per Clock
– 2 SP x SP → DP Every Two Clocks
– 2 SP x DP → DP Every Three Clocks
– 2 DP x DP → DP Every Four Clocks
• Fixed-Point Multiply Supports Two 32 x
32 Multiplies, Four 16 x 16-bit Multiplies
including Complex Multiplies, or Eight 8 x
8-Bit Multiplies per Clock Cycle
• C674x Two-Level Memory Architecture
– 32K-Byte L1P and L1D RAM/Cache
– 256K-Byte L2 Unified Mapped RAM/Caches
• DSP/EDMA Memory Management Unit
(DEMMU)
– Maps C674x DSP and EMDA TCB Memory
Accesses to System Addresses
• 512K-Bytes On-Chip Memory Controller
(OCMC) RAM
• SGX530 3D Graphics Engine (available only on
the C6A8168 device)
– Delivers up to 30 MTriangles/s
– Universal Scalable Shader Engine
– Direct3D^® Mobile, OpenGL^® ES 1.1 and 2.0,
OpenVG™ 1.0, OpenMax™ API Support
– Advanced Geometry DMA Driven Operation
– Programmable HQ Image Anti-Aliasing
• Endianness
– ARM/DSP Instructions/Data – Little Endian
• HD Video Processing Subsystem (HDVPSS)
– Two 165 MHz HD Video Capture Channels
• One 16/24-bit and One 16-bit Channel
• Each Channel Splittable Into Dual 8-bit
Capture Channels
– Two 165 MHz HD Video Display Channels
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Integra, C64x+, SmartReflex, TMS320C6000, Code Composer Studio, DSP/BIOS, XDS are trademarks of Texas Instruments.
2
Cortex, NEON are trademarks of ARM Ltd or its subsidiaries.
3
ARM, Jazelle, Thumb are registered trademarks of ARM Ltd or its subsidiaries.
4
USSE, POWERVR are trademarks of Imagination Technologies Limited.
5
OpenVG, OpenMax are trademarks of Khronos Group Inc.
6
Direct3D, Microsoft, Windows are registered trademarks of Microsoft Corporation in the United States and/or other countries.
7
I²C BUS is a registered trademark of NXP B.V. Corporation Netherlands.
8
PCI Express, PCIe are registered trademarks of PCI-SIG.
9
OpenGL is a registered trademark of Silicon Graphics International Corp. or its subsidiaries in the United States and/or other countries.
10
All other trademarks are the property of their respective owners.
11
PRODUCT PREVIEW information concerns products in the formative
or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right
to change or discontinue these products without notice.
Copyright © 2010, Texas Instruments Incorporated